c354f31b30
Add the full PCIe root port configuration. Proper initialization of the root ports depends on the correct GPIO programming including virtual wires. Do not program the CLKREQ signals in coreboot to let FSP detect and configure CLKREQ pads. Otherwise the CLKREQ pads are reprogrammed by FSP despite having GpioOverride=1. The pads that should not be touched by coreboot are left commented in the board GPIO file. CLKREQ reprogramming caused undefined behavior when ASPM and Clock PM was being enabled by coreboot on PCIe endpoints of CPU PCIe x4 slot (coreboot printed a lot of exceptions and simply halted). TEST=Boot the MSI PRO Z690-A DDR4 WiFi with all PCIe/M.2 slots populated and check if they are detected and functional in Linux. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I50199d2caf54509a72c5100acb770bf766327e7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/63656 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
17 lines
604 B
Text
17 lines
604 B
Text
CONFIG_VENDOR_MSI=y
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CONFIG_CBFS_SIZE=0x1000000
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CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
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CONFIG_TIANOCORE_BOOT_TIMEOUT=3
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CONFIG_BOARD_MSI_Z690_A_PRO_WIFI_DDR4=y
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CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
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CONFIG_PCIEXP_HOTPLUG=y
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CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G=y
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CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
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CONFIG_POST_DEVICE_PCI_PCIE=y
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CONFIG_POST_IO_PORT=0x80
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CONFIG_PAYLOAD_TIANOCORE=y
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CONFIG_TIANOCORE_REPOSITORY="https://github.com/Dasharo/edk2.git"
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CONFIG_TIANOCORE_TAG_OR_REV="origin/dasharo"
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CONFIG_TIANOCORE_CBMEM_LOGGING=y
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CONFIG_TIANOCORE_FOLLOW_BGRT_SPEC=y
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CONFIG_TIANOCORE_SD_MMC_TIMEOUT=1000
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