482af6d15c
xHCI requires special treatment of set_address since it determines the device number itself (instead of the driver, as with the other controllers). The controller also wants to validate a chosen device configuration and we need to setup additional structures for the device and the endpoints. Therefore, we add three functions to the hci_t structure, namely: set_address() finish_device_config() destroy_device() Current implementation for the Set Address request moved into generic_set_address() which is set_address() for the UHCI, OCHI and EHCI drivers. The latter two are only provided as hooks for the xHCI driver. The Set Configuration request is moved after endpoint enumeration. For all other controller drivers nothing changes, as there is no other device communication between the lines where the set_configuration() call moved. Change-Id: I6127627b9367ef573aa1a1525782bc1304ea350d Signed-off-by: Nico Huber <nico.huber@secunet.com> Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/3447 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
648 lines
21 KiB
C
648 lines
21 KiB
C
/*
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* This file is part of the libpayload project.
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*
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* Copyright (C) 2008-2010 coresystems GmbH
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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//#define USB_DEBUG
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#include <arch/virtual.h>
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#include <usb/usb.h>
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#include "uhci.h"
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#include "uhci_private.h"
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static void uhci_start (hci_t *controller);
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static void uhci_stop (hci_t *controller);
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static void uhci_reset (hci_t *controller);
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static void uhci_shutdown (hci_t *controller);
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static int uhci_bulk (endpoint_t *ep, int size, u8 *data, int finalize);
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static int uhci_control (usbdev_t *dev, direction_t dir, int drlen, void *devreq,
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int dalen, u8 *data);
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static void* uhci_create_intr_queue (endpoint_t *ep, int reqsize, int reqcount, int reqtiming);
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static void uhci_destroy_intr_queue (endpoint_t *ep, void *queue);
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static u8* uhci_poll_intr_queue (void *queue);
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#if 0
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/* dump uhci */
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static void
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uhci_dump (hci_t *controller)
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{
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usb_debug ("dump:\nUSBCMD: %x\n", uhci_reg_read16 (controller, USBCMD));
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usb_debug ("USBSTS: %x\n", uhci_reg_read16 (controller, USBSTS));
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usb_debug ("USBINTR: %x\n", uhci_reg_read16 (controller, USBINTR));
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usb_debug ("FRNUM: %x\n", uhci_reg_read16 (controller, FRNUM));
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usb_debug ("FLBASEADD: %x\n", uhci_reg_read32 (controller, FLBASEADD));
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usb_debug ("SOFMOD: %x\n", uhci_reg_read8 (controller, SOFMOD));
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usb_debug ("PORTSC1: %x\n", uhci_reg_read16 (controller, PORTSC1));
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usb_debug ("PORTSC2: %x\n", uhci_reg_read16 (controller, PORTSC2));
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}
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#endif
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static void td_dump(td_t *td)
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{
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usb_debug("+---------------------------------------------------+\n");
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if ((td->token & TD_PID_MASK) == UHCI_SETUP)
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usb_debug("|..[SETUP]..........................................|\n");
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else if ((td->token & TD_PID_MASK) == UHCI_IN)
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usb_debug("|..[IN].............................................|\n");
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else if ((td->token & TD_PID_MASK) == UHCI_OUT)
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usb_debug("|..[OUT]............................................|\n");
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else
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usb_debug("|..[]...............................................|\n");
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usb_debug("|:|============ UHCI TD at [0x%08lx] ==========|:|\n", virt_to_phys(td));
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usb_debug("|:+-----------------------------------------------+:|\n");
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usb_debug("|:| Next TD/QH [0x%08lx] |:|\n", td->ptr & ~0xFUL);
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usb_debug("|:+-----------------------------------------------+:|\n");
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usb_debug("|:| Depth/Breath [%lx] | QH/TD [%lx] | TERMINATE [%lx] |:|\n",
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(td->ptr & (1UL << 2)) >> 2, (td->ptr & (1UL << 1)) >> 1, td->ptr & 1UL);
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usb_debug("|:+-----------------------------------------------+:|\n");
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usb_debug("|:| T | Maximum Length | [%04lx] |:|\n", (td->token & (0x7FFUL << 21)) >> 21);
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usb_debug("|:| O | PID CODE | [%04lx] |:|\n", td->token & 0xFF);
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usb_debug("|:| K | Endpoint | [%04lx] |:|\n", (td->token & TD_EP_MASK) >> TD_EP_SHIFT);
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usb_debug("|:| E | Device Address | [%04lx] |:|\n", (td->token & (0x7FUL << 8)) >> 8);
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usb_debug("|:| N | Data Toggle | [%lx] |:|\n", (td->token & (1UL << 19)) >> 19);
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usb_debug("|:+-----------------------------------------------+:|\n");
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usb_debug("|:| C | Short Packet Detector | [%lx] |:|\n", (td->ctrlsts & (1UL << 29)) >> 29);
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usb_debug("|:| O | Error Counter | [%lx] |:|\n",
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(td->ctrlsts & (3UL << TD_COUNTER_SHIFT)) >> TD_COUNTER_SHIFT);
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usb_debug("|:| N | Low Speed Device | [%lx] |:|\n", (td->ctrlsts & (1UL << 26)) >> 26);
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usb_debug("|:| T | Isochronous Select | [%lx] |:|\n", (td->ctrlsts & (1UL << 25)) >> 25);
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usb_debug("|:| R | Interrupt on Complete (IOC) | [%lx] |:|\n", (td->ctrlsts & (1UL << 24)) >> 24);
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usb_debug("|:+ O ----------------------------------------+:|\n");
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usb_debug("|:| L | Active | [%lx] |:|\n", (td->ctrlsts & (1UL << 23)) >> 23);
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usb_debug("|:| & | Stalled | [%lx] |:|\n", (td->ctrlsts & (1UL << 22)) >> 22);
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usb_debug("|:| S | Data Buffer Error | [%lx] |:|\n", (td->ctrlsts & (1UL << 21)) >> 21);
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usb_debug("|:| T | Bubble Detected | [%lx] |:|\n", (td->ctrlsts & (1UL << 20)) >> 20);
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usb_debug("|:| A | NAK Received | [%lx] |:|\n", (td->ctrlsts & (1UL << 19)) >> 19);
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usb_debug("|:| T | CRC/Timeout Error | [%lx] |:|\n", (td->ctrlsts & (1UL << 18)) >> 18);
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usb_debug("|:| U | Bitstuff Error | [%lx] |:|\n", (td->ctrlsts & (1UL << 17)) >> 17);
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usb_debug("|:| S ----------------------------------------|:|\n");
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usb_debug("|:| | Actual Length | [%04lx] |:|\n", td->ctrlsts & 0x7FFUL);
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usb_debug("|:+-----------------------------------------------+:|\n");
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usb_debug("|:| Buffer pointer [0x%08lx] |:|\n", td->bufptr);
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usb_debug("|:|-----------------------------------------------|:|\n");
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usb_debug("|...................................................|\n");
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usb_debug("+---------------------------------------------------+\n");
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}
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static void
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uhci_reset (hci_t *controller)
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{
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/* reset */
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uhci_reg_write16 (controller, USBCMD, 4); /* Global Reset */
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mdelay (50); /* uhci spec 2.1.1: at least 10ms */
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uhci_reg_write16 (controller, USBCMD, 0);
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mdelay (10);
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uhci_reg_write16 (controller, USBCMD, 2); /* Host Controller Reset */
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/* wait for controller to finish reset */
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/* TOTEST: how long to wait? 100ms for now */
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int timeout = 200; /* time out after 200 * 500us == 100ms */
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while (((uhci_reg_read16 (controller, USBCMD) & 2) != 0) && timeout--)
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udelay (500);
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if (timeout < 0)
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usb_debug ("Warning: uhci: host controller reset timed out.\n");
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}
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static void
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uhci_reinit (hci_t *controller)
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{
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uhci_reg_write32 (controller, FLBASEADD,
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(u32) virt_to_phys (UHCI_INST (controller)->
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framelistptr));
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//usb_debug ("framelist at %p\n",UHCI_INST(controller)->framelistptr);
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/* disable irqs */
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uhci_reg_write16 (controller, USBINTR, 0);
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/* reset framelist index */
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uhci_reg_write16 (controller, FRNUM, 0);
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uhci_reg_write16(controller, USBCMD,
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uhci_reg_read16(controller, USBCMD) | 0xc0); // max packets, configure flag
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uhci_start (controller);
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}
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hci_t *
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uhci_init (pcidev_t addr)
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{
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int i;
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u16 reg16;
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hci_t *controller = new_controller ();
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if (!controller)
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fatal("Could not create USB controller instance.\n");
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controller->instance = malloc (sizeof (uhci_t));
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if(!controller->instance)
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fatal("Not enough memory creating USB controller instance.\n");
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controller->type = UHCI;
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controller->start = uhci_start;
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controller->stop = uhci_stop;
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controller->reset = uhci_reset;
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controller->init = uhci_reinit;
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controller->shutdown = uhci_shutdown;
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controller->bulk = uhci_bulk;
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controller->control = uhci_control;
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controller->set_address = generic_set_address;
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controller->finish_device_config = NULL;
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controller->destroy_device = NULL;
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controller->create_intr_queue = uhci_create_intr_queue;
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controller->destroy_intr_queue = uhci_destroy_intr_queue;
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controller->poll_intr_queue = uhci_poll_intr_queue;
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for (i = 0; i < 128; i++) {
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controller->devices[i] = 0;
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}
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init_device_entry (controller, 0);
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UHCI_INST (controller)->roothub = controller->devices[0];
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controller->bus_address = addr;
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controller->reg_base = pci_read_config32 (controller->bus_address, 0x20) & ~1; /* ~1 clears the register type indicator that is set to 1 for IO space */
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/* kill legacy support handler */
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uhci_stop (controller);
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mdelay (1);
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uhci_reg_write16 (controller, USBSTS, 0x3f);
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reg16 = pci_read_config16(controller->bus_address, 0xc0);
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reg16 &= 0xdf80;
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pci_write_config16 (controller->bus_address, 0xc0, reg16);
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UHCI_INST (controller)->framelistptr = memalign (0x1000, 1024 * sizeof (flistp_t)); /* 4kb aligned to 4kb */
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if (! UHCI_INST (controller)->framelistptr)
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fatal("Not enough memory for USB frame list pointer.\n");
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memset (UHCI_INST (controller)->framelistptr, 0,
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1024 * sizeof (flistp_t));
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/* According to the *BSD UHCI code, this one is needed on some
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PIIX chips, because otherwise they misbehave. It must be
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added to the last chain.
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FIXME: this leaks, if the driver should ever be reinited
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for some reason. Not a problem now.
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*/
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td_t *antiberserk = memalign(16, sizeof(td_t));
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if (!antiberserk)
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fatal("Not enough memory for chipset workaround.\n");
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memset(antiberserk, 0, sizeof(td_t));
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UHCI_INST (controller)->qh_prei = memalign (16, sizeof (qh_t));
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UHCI_INST (controller)->qh_intr = memalign (16, sizeof (qh_t));
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UHCI_INST (controller)->qh_data = memalign (16, sizeof (qh_t));
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UHCI_INST (controller)->qh_last = memalign (16, sizeof (qh_t));
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if (! UHCI_INST (controller)->qh_prei ||
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! UHCI_INST (controller)->qh_intr ||
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! UHCI_INST (controller)->qh_data ||
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! UHCI_INST (controller)->qh_last)
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fatal("Not enough memory for USB controller queues.\n");
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UHCI_INST (controller)->qh_prei->headlinkptr =
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virt_to_phys (UHCI_INST (controller)->qh_intr) | FLISTP_QH;
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UHCI_INST (controller)->qh_prei->elementlinkptr = 0 | FLISTP_TERMINATE;
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UHCI_INST (controller)->qh_intr->headlinkptr =
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virt_to_phys (UHCI_INST (controller)->qh_data) | FLISTP_QH;
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UHCI_INST (controller)->qh_intr->elementlinkptr = 0 | FLISTP_TERMINATE;
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UHCI_INST (controller)->qh_data->headlinkptr =
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virt_to_phys (UHCI_INST (controller)->qh_last) | FLISTP_QH;
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UHCI_INST (controller)->qh_data->elementlinkptr = 0 | FLISTP_TERMINATE;
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UHCI_INST (controller)->qh_last->headlinkptr = virt_to_phys (UHCI_INST (controller)->qh_data) | FLISTP_TERMINATE;
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UHCI_INST (controller)->qh_last->elementlinkptr = virt_to_phys (antiberserk) | FLISTP_TERMINATE;
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for (i = 0; i < 1024; i++) {
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UHCI_INST (controller)->framelistptr[i] =
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virt_to_phys (UHCI_INST (controller)->qh_prei) | FLISTP_QH;
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}
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controller->devices[0]->controller = controller;
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controller->devices[0]->init = uhci_rh_init;
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controller->devices[0]->init (controller->devices[0]);
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uhci_reset (controller);
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uhci_reinit (controller);
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return controller;
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}
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static void
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uhci_shutdown (hci_t *controller)
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{
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if (controller == 0)
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return;
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detach_controller (controller);
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UHCI_INST (controller)->roothub->destroy (UHCI_INST (controller)->
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roothub);
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uhci_reg_write16(controller, USBCMD,
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uhci_reg_read16(controller, USBCMD) & 0); // stop work
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free (UHCI_INST (controller)->framelistptr);
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free (UHCI_INST (controller)->qh_prei);
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free (UHCI_INST (controller)->qh_intr);
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free (UHCI_INST (controller)->qh_data);
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free (UHCI_INST (controller)->qh_last);
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free (UHCI_INST (controller));
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free (controller);
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}
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static void
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uhci_start (hci_t *controller)
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{
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uhci_reg_write16(controller, USBCMD,
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uhci_reg_read16(controller, USBCMD) | 1); // start work on schedule
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}
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static void
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uhci_stop (hci_t *controller)
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{
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uhci_reg_write16(controller, USBCMD,
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uhci_reg_read16(controller, USBCMD) & ~1); // stop work on schedule
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}
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#define GET_TD(x) ((void*)(((unsigned int)(x))&~0xf))
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static td_t *
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wait_for_completed_qh (hci_t *controller, qh_t *qh)
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{
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int timeout = 1000; /* max 30 ms. */
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void *current = GET_TD (qh->elementlinkptr);
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while (((qh->elementlinkptr & FLISTP_TERMINATE) == 0) && (timeout-- > 0)) {
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if (current != GET_TD (qh->elementlinkptr)) {
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current = GET_TD (qh->elementlinkptr);
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timeout = 1000;
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}
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uhci_reg_write16(controller, USBSTS,
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uhci_reg_read16(controller, USBSTS) | 0); // clear resettable registers
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udelay (30);
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}
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return (GET_TD (qh->elementlinkptr) ==
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0) ? 0 : GET_TD (phys_to_virt (qh->elementlinkptr));
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}
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static int
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maxlen (int size)
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{
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return (size - 1) & 0x7ff;
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}
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static int
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min (int a, int b)
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{
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if (a < b)
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return a;
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else
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return b;
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}
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static int
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uhci_control (usbdev_t *dev, direction_t dir, int drlen, void *devreq, int dalen,
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unsigned char *data)
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{
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int endp = 0; /* this is control: always 0 */
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int mlen = dev->endpoints[0].maxpacketsize;
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int count = (2 + (dalen + mlen - 1) / mlen);
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unsigned short req = ((unsigned short *) devreq)[0];
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int i;
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td_t *tds = memalign (16, sizeof (td_t) * count);
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memset (tds, 0, sizeof (td_t) * count);
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count--; /* to compensate for 0-indexed array */
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for (i = 0; i < count; i++) {
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tds[i].ptr = virt_to_phys (&tds[i + 1]) | TD_DEPTH_FIRST;
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}
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tds[count].ptr = 0 | TD_DEPTH_FIRST | TD_TERMINATE;
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tds[0].token = UHCI_SETUP |
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dev->address << TD_DEVADDR_SHIFT |
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endp << TD_EP_SHIFT |
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TD_TOGGLE_DATA0 |
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maxlen(drlen) << TD_MAXLEN_SHIFT;
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tds[0].bufptr = virt_to_phys (devreq);
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tds[0].ctrlsts = (3 << TD_COUNTER_SHIFT) |
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(dev->speed?TD_LOWSPEED:0) |
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TD_STATUS_ACTIVE;
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int toggle = 1;
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for (i = 1; i < count; i++) {
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switch (dir) {
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case SETUP: tds[i].token = UHCI_SETUP; break;
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case IN: tds[i].token = UHCI_IN; break;
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case OUT: tds[i].token = UHCI_OUT; break;
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}
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tds[i].token |= dev->address << TD_DEVADDR_SHIFT |
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endp << TD_EP_SHIFT |
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maxlen (min (mlen, dalen)) << TD_MAXLEN_SHIFT |
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toggle << TD_TOGGLE_SHIFT;
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tds[i].bufptr = virt_to_phys (data);
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tds[i].ctrlsts = (3 << TD_COUNTER_SHIFT) |
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(dev->speed?TD_LOWSPEED:0) |
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TD_STATUS_ACTIVE;
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toggle ^= 1;
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dalen -= mlen;
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data += mlen;
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}
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tds[count].token = ((dir == OUT) ? UHCI_IN : UHCI_OUT) |
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dev->address << TD_DEVADDR_SHIFT |
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endp << TD_EP_SHIFT |
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maxlen(0) << TD_MAXLEN_SHIFT |
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TD_TOGGLE_DATA1;
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tds[count].bufptr = 0;
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tds[count].ctrlsts = (0 << TD_COUNTER_SHIFT) | /* as Linux 2.4.10 does */
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(dev->speed?TD_LOWSPEED:0) |
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TD_STATUS_ACTIVE;
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UHCI_INST (dev->controller)->qh_data->elementlinkptr =
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virt_to_phys (tds) & ~(FLISTP_QH | FLISTP_TERMINATE);
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td_t *td = wait_for_completed_qh (dev->controller,
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UHCI_INST (dev->controller)->
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qh_data);
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int result;
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if (td == 0) {
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result = 0;
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} else {
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usb_debug ("control packet, req %x\n", req);
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td_dump (td);
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result = 1;
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}
|
|
free (tds);
|
|
return result;
|
|
}
|
|
|
|
static td_t *
|
|
create_schedule (int numpackets)
|
|
{
|
|
if (numpackets == 0)
|
|
return 0;
|
|
td_t *tds = memalign (16, sizeof (td_t) * numpackets);
|
|
memset (tds, 0, sizeof (td_t) * numpackets);
|
|
int i;
|
|
for (i = 0; i < numpackets; i++) {
|
|
tds[i].ptr = virt_to_phys (&tds[i + 1]) | TD_DEPTH_FIRST;
|
|
}
|
|
tds[numpackets - 1].ptr = 0 | TD_TERMINATE;
|
|
return tds;
|
|
}
|
|
|
|
static void
|
|
fill_schedule (td_t *td, endpoint_t *ep, int length, unsigned char *data,
|
|
int *toggle)
|
|
{
|
|
switch (ep->direction) {
|
|
case IN: td->token = UHCI_IN; break;
|
|
case OUT: td->token = UHCI_OUT; break;
|
|
case SETUP: td->token = UHCI_SETUP; break;
|
|
}
|
|
td->token |= ep->dev->address << TD_DEVADDR_SHIFT |
|
|
(ep->endpoint & 0xf) << TD_EP_SHIFT |
|
|
maxlen (length) << TD_MAXLEN_SHIFT |
|
|
(*toggle & 1) << TD_TOGGLE_SHIFT;
|
|
td->bufptr = virt_to_phys (data);
|
|
td->ctrlsts = ((ep->direction == SETUP?3:0) << TD_COUNTER_SHIFT) |
|
|
(ep->dev->speed?TD_LOWSPEED:0) |
|
|
TD_STATUS_ACTIVE;
|
|
*toggle ^= 1;
|
|
}
|
|
|
|
static int
|
|
run_schedule (usbdev_t *dev, td_t *td)
|
|
{
|
|
UHCI_INST (dev->controller)->qh_data->elementlinkptr =
|
|
virt_to_phys (td) & ~(FLISTP_QH | FLISTP_TERMINATE);
|
|
td = wait_for_completed_qh (dev->controller,
|
|
UHCI_INST (dev->controller)->qh_data);
|
|
if (td == 0) {
|
|
return 0;
|
|
} else {
|
|
td_dump (td);
|
|
return 1;
|
|
}
|
|
}
|
|
|
|
/* finalize == 1: if data is of packet aligned size, add a zero length packet */
|
|
static int
|
|
uhci_bulk (endpoint_t *ep, int size, u8 *data, int finalize)
|
|
{
|
|
int maxpsize = ep->maxpacketsize;
|
|
if (maxpsize == 0)
|
|
fatal("MaxPacketSize == 0!!!");
|
|
int numpackets = (size + maxpsize - 1) / maxpsize;
|
|
if (finalize && ((size % maxpsize) == 0)) {
|
|
numpackets++;
|
|
}
|
|
if (numpackets == 0)
|
|
return 0;
|
|
td_t *tds = create_schedule (numpackets);
|
|
int i = 0, toggle = ep->toggle;
|
|
while ((size > 0) || ((size == 0) && (finalize != 0))) {
|
|
fill_schedule (&tds[i], ep, min (size, maxpsize), data,
|
|
&toggle);
|
|
i++;
|
|
data += maxpsize;
|
|
size -= maxpsize;
|
|
}
|
|
if (run_schedule (ep->dev, tds) == 1) {
|
|
usb_debug("Stalled. Trying to clean up.\n");
|
|
clear_stall (ep);
|
|
free (tds);
|
|
return 1;
|
|
}
|
|
ep->toggle = toggle;
|
|
free (tds);
|
|
return 0;
|
|
}
|
|
|
|
typedef struct {
|
|
qh_t *qh;
|
|
td_t *tds;
|
|
td_t *last_td;
|
|
u8 *data;
|
|
int lastread;
|
|
int total;
|
|
int reqsize;
|
|
} intr_q;
|
|
|
|
/* create and hook-up an intr queue into device schedule */
|
|
static void*
|
|
uhci_create_intr_queue (endpoint_t *ep, int reqsize, int reqcount, int reqtiming)
|
|
{
|
|
u8 *data = malloc(reqsize*reqcount);
|
|
td_t *tds = memalign(16, sizeof(td_t) * reqcount);
|
|
qh_t *qh = memalign(16, sizeof(qh_t));
|
|
|
|
if (!data || !tds || !qh)
|
|
fatal("Not enough memory to create USB intr queue prerequisites.\n");
|
|
|
|
qh->elementlinkptr = virt_to_phys(tds);
|
|
|
|
intr_q *q = malloc(sizeof(intr_q));
|
|
if (!q)
|
|
fatal("Not enough memory to create USB intr queue.\n");
|
|
q->qh = qh;
|
|
q->tds = tds;
|
|
q->data = data;
|
|
q->lastread = 0;
|
|
q->total = reqcount;
|
|
q->reqsize = reqsize;
|
|
q->last_td = &tds[reqcount - 1];
|
|
|
|
memset (tds, 0, sizeof (td_t) * reqcount);
|
|
int i;
|
|
for (i = 0; i < reqcount; i++) {
|
|
tds[i].ptr = virt_to_phys (&tds[i + 1]);
|
|
|
|
switch (ep->direction) {
|
|
case IN: tds[i].token = UHCI_IN; break;
|
|
case OUT: tds[i].token = UHCI_OUT; break;
|
|
case SETUP: tds[i].token = UHCI_SETUP; break;
|
|
}
|
|
tds[i].token |= ep->dev->address << TD_DEVADDR_SHIFT |
|
|
(ep->endpoint & 0xf) << TD_EP_SHIFT |
|
|
maxlen (reqsize) << TD_MAXLEN_SHIFT |
|
|
(ep->toggle & 1) << TD_TOGGLE_SHIFT;
|
|
tds[i].bufptr = virt_to_phys (data);
|
|
tds[i].ctrlsts = (0 << TD_COUNTER_SHIFT) |
|
|
(ep->dev->speed?TD_LOWSPEED:0) |
|
|
TD_STATUS_ACTIVE;
|
|
ep->toggle ^= 1;
|
|
data += reqsize;
|
|
}
|
|
tds[reqcount - 1].ptr = 0 | TD_TERMINATE;
|
|
|
|
/* insert QH into framelist */
|
|
uhci_t *const uhcic = UHCI_INST(ep->dev->controller);
|
|
const u32 def_ptr = virt_to_phys(uhcic->qh_prei) | FLISTP_QH;
|
|
int nothing_placed = 1;
|
|
qh->headlinkptr = def_ptr;
|
|
for (i = 0; i < 1024; i += reqtiming) {
|
|
/* advance to the next free position */
|
|
while ((i < 1024) && (uhcic->framelistptr[i] != def_ptr)) ++i;
|
|
if (i < 1024) {
|
|
uhcic->framelistptr[i] = virt_to_phys(qh) | FLISTP_QH;
|
|
nothing_placed = 0;
|
|
}
|
|
}
|
|
if (nothing_placed) {
|
|
usb_debug("Error: Failed to place UHCI interrupt queue "
|
|
"head into framelist: no space left\n");
|
|
uhci_destroy_intr_queue(ep, q);
|
|
return NULL;
|
|
}
|
|
|
|
return q;
|
|
}
|
|
|
|
/* remove queue from device schedule, dropping all data that came in */
|
|
static void
|
|
uhci_destroy_intr_queue (endpoint_t *ep, void *q_)
|
|
{
|
|
intr_q *const q = (intr_q*)q_;
|
|
|
|
/* remove QH from framelist */
|
|
uhci_t *const uhcic = UHCI_INST(ep->dev->controller);
|
|
const u32 qh_ptr = virt_to_phys(q->qh) | FLISTP_QH;
|
|
const u32 def_ptr = virt_to_phys(uhcic->qh_prei) | FLISTP_QH;
|
|
int i;
|
|
for (i = 0; i < 1024; ++i) {
|
|
if (uhcic->framelistptr[i] == qh_ptr)
|
|
uhcic->framelistptr[i] = def_ptr;
|
|
}
|
|
|
|
free(q->data);
|
|
free(q->tds);
|
|
free(q->qh);
|
|
free(q);
|
|
}
|
|
|
|
/* read one intr-packet from queue, if available. extend the queue for new input.
|
|
return NULL if nothing new available.
|
|
Recommended use: while (data=poll_intr_queue(q)) process(data);
|
|
*/
|
|
static u8*
|
|
uhci_poll_intr_queue (void *q_)
|
|
{
|
|
intr_q *q = (intr_q*)q_;
|
|
if ((q->tds[q->lastread].ctrlsts & TD_STATUS_ACTIVE) == 0) {
|
|
int current = q->lastread;
|
|
int previous;
|
|
if (q->lastread == 0) {
|
|
previous = q->total - 1;
|
|
} else {
|
|
previous = q->lastread - 1;
|
|
}
|
|
q->tds[previous].ctrlsts &= ~TD_STATUS_MASK;
|
|
q->tds[previous].ptr = 0 | TD_TERMINATE;
|
|
if (q->last_td != &q->tds[previous]) {
|
|
q->last_td->ptr = virt_to_phys(&q->tds[previous]) & ~TD_TERMINATE;
|
|
q->last_td = &q->tds[previous];
|
|
}
|
|
q->tds[previous].ctrlsts |= TD_STATUS_ACTIVE;
|
|
q->lastread = (q->lastread + 1) % q->total;
|
|
if (!(q->tds[current].ctrlsts & TD_STATUS_MASK))
|
|
return &q->data[current*q->reqsize];
|
|
}
|
|
/* reset queue if we fully processed it after underrun */
|
|
else if (q->qh->elementlinkptr & FLISTP_TERMINATE) {
|
|
usb_debug("resetting underrun uhci interrupt queue.\n");
|
|
q->qh->elementlinkptr = virt_to_phys(q->tds + q->lastread);
|
|
}
|
|
return NULL;
|
|
}
|
|
|
|
void
|
|
uhci_reg_write32 (hci_t *ctrl, usbreg reg, u32 value)
|
|
{
|
|
outl (value, ctrl->reg_base + reg);
|
|
}
|
|
|
|
u32
|
|
uhci_reg_read32 (hci_t *ctrl, usbreg reg)
|
|
{
|
|
return inl (ctrl->reg_base + reg);
|
|
}
|
|
|
|
void
|
|
uhci_reg_write16 (hci_t *ctrl, usbreg reg, u16 value)
|
|
{
|
|
outw (value, ctrl->reg_base + reg);
|
|
}
|
|
|
|
u16
|
|
uhci_reg_read16 (hci_t *ctrl, usbreg reg)
|
|
{
|
|
return inw (ctrl->reg_base + reg);
|
|
}
|
|
|
|
void
|
|
uhci_reg_write8 (hci_t *ctrl, usbreg reg, u8 value)
|
|
{
|
|
outb (value, ctrl->reg_base + reg);
|
|
}
|
|
|
|
u8
|
|
uhci_reg_read8 (hci_t *ctrl, usbreg reg)
|
|
{
|
|
return inb (ctrl->reg_base + reg);
|
|
}
|