coreboot-kgpe-d16/src/arch/mips
Vadim Bendebury b92e54333f mips: do not place branch instructions in branch delay slot
A branch instruction in a branch delay slot confuses the execution
pipeline and causes an exception.

bootblock.S was written 'by hand', has a branch instruction in branch
delay slot and includes '.set noreorder' directive, which causes it to
crash when trying to branch to main().

Adding a nop instruction fixes the problem. Also adding a nop after
the last branch in the file just in case main() returns and the object
linked next starts with a branch.

BUG=chrome-os-partner:31438
TEST=Running on the simulator can reach main() now

Change-Id: I0882b2eb5ce426f5a311018ffbb6f37a2ca64d98
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/221421
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9183
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2015-04-02 21:43:16 +02:00
..
include mips: bring payload execution to current standards 2015-03-30 20:41:24 +02:00
ashldi3.c
boot.c mips: bring payload execution to current standards 2015-03-30 20:41:24 +02:00
bootblock.ld mips: Simplify architecture specific Makefile.inc 2015-03-30 20:41:20 +02:00
bootblock.S mips: do not place branch instructions in branch delay slot 2015-04-02 21:43:16 +02:00
bootblock_simple.c mips: don't open code romstage loading 2015-03-31 07:55:25 +02:00
Kconfig mips: add verstage configuration 2015-03-29 22:38:53 +02:00
Makefile.inc imgtec/pistachio: Bring uart driver to modern standards 2015-03-30 20:41:22 +02:00
ramstage.ld mips: Simplify architecture specific Makefile.inc 2015-03-30 20:41:20 +02:00
romstage.ld mips: Simplify architecture specific Makefile.inc 2015-03-30 20:41:20 +02:00
stages.c
tables.c mips: fix write_table 2015-03-30 20:41:23 +02:00
timer.c