a2f8eb98f5
Changes: - Get rid of the south_station mainboard specific code and use the platform generic function wrapper that was added in change http://review.coreboot.org/#/c/2497/ AMD f14: Add SPD read functions to wrapper code - Move DIMM addresses into devicetree.cb - Add the ASF init that used to be in the SPD read code into mainboard_enable() Notes: - The DIMM reads only happen in romstage, so the function is not available in ramstage. Point the read-SPD callback to a generic function in ramstage. Change-Id: If4291d25ea81bf375f55b64c07c223a847a211d0 Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com> Reviewed-on: http://review.coreboot.org/2608 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
97 lines
3 KiB
C
97 lines
3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <arch/io.h>
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#include <cpu/x86/msr.h>
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#include <southbridge/amd/sb800/sb800.h>
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#include <cpu/amd/mtrr.h>
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#include <device/pci_def.h>
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#include <delay.h>
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#include "SBPLATFORM.h" /* Platfrom Specific Definitions */
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void set_pcie_reset(void);
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void set_pcie_dereset(void);
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/**
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* TODO
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* SB CIMx callback
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*/
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void set_pcie_reset(void)
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{
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}
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/**
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* TODO
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* mainboard specific SB CIMx callback
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*/
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void set_pcie_dereset(void)
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{
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}
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/**
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* Southstation using SB GPIO 17/18 to control the Red/Green LED
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* These two LEDs can be used to show the OS booting status.
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*/
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static void southstation_led_init(void)
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{
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#define GPIO_FUNCTION 2 //GPIO function
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#define SB_GPIO_REG17 17 //Red Light
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#define SB_GPIO_REG18 18 //Green Light
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/* multi-function pins switch to GPIO0-35 */
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RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 1);
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/* select IOMux to function2, corresponds to GPIO */
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RWMEM(ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG17, AccWidthUint8, ~(BIT0 | BIT1), GPIO_FUNCTION);
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RWMEM(ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG18, AccWidthUint8, ~(BIT0 | BIT1), GPIO_FUNCTION);
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/* Lighting test */
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RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG17, AccWidthUint8, ~(0xFF), 0x08); //output high
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RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG18, AccWidthUint8, ~(0xFF), 0x08);
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mdelay(100);
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RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG17, AccWidthUint8, ~(0xFF), 0x48); //output low
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RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG18, AccWidthUint8, ~(0xFF), 0x48);
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}
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/**********************************************
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* Enable the dedicated functions of the board.
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**********************************************/
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static void mainboard_enable(device_t dev)
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{
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printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
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southstation_led_init();
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/*
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* Initialize ASF registers to an arbitrary address because someone
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* long ago set things up this way inside the SPD read code. The
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* SPD read code has been made generic and moved out of the board
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* directory, so the ASF init is being done here.
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*/
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pm_iowrite(0x29, 0x80);
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pm_iowrite(0x28, 0x61);
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}
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struct chip_operations mainboard_ops = {
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.enable_dev = mainboard_enable,
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};
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