coreboot-kgpe-d16/src/vendorcode
Ronak Kanabar c4813ea260 vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2162_00
The headers added are generated as per FSP v2162_00.
Previous FSP version was v2117_00.
Changes Include:
- Adjust UPD Offset in FspmUpd.h and FspsUpd.h
- Remove DisableDimmMc*Ch* Upds in FspmUpd.h
- Add DisableMc*Ch* Upds in FspmUpd.h
- Few UPDs description update in FspmUpd.h and FspsUpd.h

Change DisableDimmMc*Ch* to DisableMc*Ch* in meminit.c to avoid
compilation failure other change related to UPDs name change will be
part of next patch in relation chain.

BUG=b:187189546
BRANCH=None
TEST=Build and boot ADLRVP using all the patch in relation chain.

Change-Id: Ic8d7980146f1bfc96472ef504cf9f16eee63a13e
Cq-Depend: chrome-internal:3831865, chrome-internal:3831864, chrome-internal:3831913
Cq-Depend: chromium:TODO
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54083
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-16 22:17:26 +00:00
..
amd vc/amd/pi/00660F01: Remove unused code and directory 2021-05-12 14:54:28 +00:00
cavium src: use ARRAY_SIZE where possible 2021-02-15 11:30:40 +00:00
eltan vc/eltan/security/mboot/Kconfig: Add dependency of VBOOT 2021-04-06 07:01:31 +00:00
google mb/google: Move ECFW_RW setting for non-ChromeEC boards 2021-04-30 06:48:56 +00:00
intel vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2162_00 2021-05-16 22:17:26 +00:00
mediatek vendor/mediatek: Add MT8195 dram initialization code 2021-05-14 04:00:38 +00:00
siemens cbfs: Simplify load/map API names, remove type arguments 2020-12-02 22:13:17 +00:00
Makefile.inc soc/mediatek/mt8192: initialize DRAM using vendor reference code 2021-03-08 03:15:43 +00:00