7837c203d6
This patch cleans soc/intel/{apollolake/cannonlake/skylake} by moving
common soc code into common/block/p2sb.
BUG=b:78109109
BRANCH=none
TEST=Build and boot KBL/CNL/APL platform.
Change-Id: Ie9fd933d155b3fcd0d616b41cdf042cefe2c649a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
43 lines
1.2 KiB
C
43 lines
1.2 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <intelblocks/p2sb.h>
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void p2sb_soc_get_sb_mask(uint32_t *ep_mask, size_t count)
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{
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uint32_t mask;
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if (count != P2SB_EP_MASK_MAX_REG) {
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printk(BIOS_ERR, "Unable to program EPMASK registers\n");
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return;
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}
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/* Remove the host accessing right to PSF register range.
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* Set p2sb PCI offset EPMASK5 [29, 28, 27, 26] to disable Sideband
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* access for PCI Root Bridge.
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*/
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mask = (1 << 29) | (1 << 28) | (1 << 27) | (1 << 26);
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ep_mask[P2SB_EP_MASK_5_REG] = mask;
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/*
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* Set p2sb PCI offset EPMASK7 [31, 30] to disable Sideband
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* access for Broadcast and Multicast.
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*/
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mask = (1 << 31) | (1 << 30);
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ep_mask[P2SB_EP_MASK_7_REG] = mask;
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}
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