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Peter Stuge c49ae3c655 Revert "PC Engines ALIX.1C: Add CMOS defaults." 
Revert commit f90071faee [1] as
it was merged without its dependencies and therefore the source
tree currently does not build [2][3].

        OPTION     option_table.h
        GEN        build.h
        SCONFIG    mainboard/pcengines/alix1c/devicetree.cb
        CC         arch/x86/lib/cbfs_and_run.romstage.o
        CC         arch/x86/lib/memcpy.romstage.o
        CC         arch/x86/lib/memset.romstage.o
        CC         arch/x86/lib/rom_media.romstage.o
        CC         arch/x86/lib/romstage_console.romstage.o
        CC         console/die.romstage.o
        CC         console/post.romstage.o
        CC         console/vtxprintf.romstage.o
        CC         device/device_romstage.romstage.o
        CC         lib/cbfs.romstage.o
        CC         lib/compute_ip_checksum.romstage.o
        CC         lib/gcc.romstage.o
        CC         lib/lzma.romstage.o
        CC         lib/memchr.romstage.o
        CC         lib/memcmp.romstage.o
        CC         lib/memmove.romstage.o
        CC         lib/ramtest.romstage.o
        CC         lib/uart8250.romstage.o
        CC         southbridge/amd/cs5536/smbus.romstage.o
        ROMCC      generated/bootblock.inc
        GEN        generated/bootblock.ld
    make: *** No rule to make target `nvramtool', needed by `coreboot-builds/pcengines_alix1c/coreboot.pre1'.  Stop.
    make: *** Waiting for unfinished jobs....
        OPTION     cmos_layout.bin

[1] http://review.coreboot.org/#/c/3229/
[2] http://www.coreboot.org/pipermail/coreboot/2013-May/075864.html
[3] http://qa.coreboot.org/job/coreboot-gerrit/6251/testReport/junit/(root)/board/i386_pcengines_alix1c/

Change-Id: I4764d90c39ccdb4dc7e7a9aef7525c306614e1a8
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/3245
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
 		2013-05-12 20:42:20 +02:00
3rdparty@ba8caa30bd Update 3rdparty mark to latest repository 2013-03-15 19:09:08 +01:00
documentation Get rid of MAXIMUM_CONSOLE_LOGLEVEL; compile all messages into the coreboot binary 2013-05-10 17:33:49 +02:00
payloads cbfs_core.c: make cfbs searches even less verbose 2013-05-08 05:02:13 +02:00
src Revert "PC Engines ALIX.1C: Add CMOS defaults." 2013-05-12 20:42:20 +02:00
util romcc: support attribute((packed)) 2013-05-10 19:33:00 +02:00
.gitignore add a few entries to .gitignore 2013-01-10 22:51:20 +01:00
.gitmodules gitmodules: Ignore 3rdparty in "diff family" 2013-03-16 04:07:14 +01:00
.gitreview add .gitreview 2012-11-01 23:13:39 +01:00
COPYING update license template. 2006-08-12 22:03:36 +00:00
Makefile build system: Retire REQUIRES_BLOB 2013-02-19 11:00:41 +01:00
Makefile.inc rmodule: add rmodules class and new type 2013-03-18 20:46:40 +01:00
README Update README with newer version of the text from the web page 2011-06-15 10:16:33 +02:00

README 

-------------------------------------------------------------------------------
coreboot README
-------------------------------------------------------------------------------

coreboot is a Free Software project aimed at replacing the proprietary BIOS
(firmware) found in most computers.  coreboot performs a little bit of
hardware initialization and then executes additional boot logic, called a
payload.

With the separation of hardware initialization and later boot logic,
coreboot can scale from specialized applications that run directly
firmware, run operating systems in flash, load custom
bootloaders, or implement firmware standards, like PC BIOS services or
UEFI. This allows for systems to only include the features necessary
in the target application, reducing the amount of code and flash space
required.

coreboot was formerly known as LinuxBIOS.


Payloads
--------

After the basic initialization of the hardware has been performed, any
desired "payload" can be started by coreboot.

See http://www.coreboot.org/Payloads for a list of supported payloads.


Supported Hardware
------------------

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

 * http://www.coreboot.org/Supported_Motherboards
 * http://www.coreboot.org/Supported_Chipsets_and_Devices


Build Requirements
------------------

 * gcc / g++
 * make

Optional:

 * doxygen (for generating/viewing documentation)
 * iasl (for targets with ACPI support)
 * gdb (for better debugging facilities on some targets)
 * ncurses (for 'make menuconfig')
 * flex and bison (for regenerating parsers)


Building coreboot
-----------------

Please consult http://www.coreboot.org/Build_HOWTO for details.


Testing coreboot Without Modifying Your Hardware
------------------------------------------------

If you want to test coreboot without any risks before you really decide
to use it on your hardware, you can use the QEMU system emulator to run
coreboot virtually in QEMU.

Please see http://www.coreboot.org/QEMU for details.


Website and Mailing List
------------------------

Further details on the project, a FAQ, many HOWTOs, news, development
guidelines and more can be found on the coreboot website:

  http://www.coreboot.org

You can contact us directly on the coreboot mailing list:

  http://www.coreboot.org/Mailinglist


Copyright and License
---------------------

The copyright on coreboot is owned by quite a large number of individual
developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL).
Some files are licensed under the "GPL (version 2, or any later version)",
and some files are licensed under the "GPL, version 2". For some parts, which
were derived from other projects, other (GPL-compatible) licenses may apply.
Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.