76cedd2c29
This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 3/5 which basically is generated by running the following command: $ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g' BUG=b:155428745 Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
54 lines
1.2 KiB
C
54 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* This file is part of the coreboot project. */
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#include <acpi/acpi.h>
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#include <console/console.h>
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#include <cpu/x86/smm.h>
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#include <ec/google/chromeec/smm.h>
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#include <soc/iomap.h>
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#include <soc/nvs.h>
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#include <soc/pm.h>
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#include <intelblocks/smihandler.h>
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#include "ec.h"
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#include "gpio.h"
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int mainboard_io_trap_handler(int smif)
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{
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switch (smif) {
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case 0x99:
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printk(BIOS_DEBUG, "Sample\n");
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smm_get_gnvs()->smif = 0;
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break;
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default:
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return 0;
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}
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/* On success, the IO Trap Handler returns 0
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* On failure, the IO Trap Handler returns a value != 0
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*
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* For now, we force the return value to 0 and log all traps to
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* see what's going on.
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*/
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return 1;
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}
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void mainboard_smi_gpi_handler(const struct gpi_status *sts)
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{
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if (gpi_status_get(sts, EC_SMI_GPI))
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chromeec_smi_process_events();
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}
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void mainboard_smi_sleep(u8 slp_typ)
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{
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if (CONFIG(EC_GOOGLE_CHROMEEC))
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chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
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MAINBOARD_EC_S5_WAKE_EVENTS);
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}
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int mainboard_smi_apmc(u8 apmc)
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{
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if (CONFIG(EC_GOOGLE_CHROMEEC))
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chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS,
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MAINBOARD_EC_SMI_EVENTS);
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return 0;
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}
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