869ac71483
This reverts commit c04871a398.
Reason for revert: Many apu2 users reported issues with PCIe modules
detection in mPCIe2 slot (4x GFX PCIe). The regression was not caught
by 3mdeb validation stands and hardware configuration.
Change-Id: I609bf4b27c88a9adf676d576169f5ca26726ee86
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40147
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
81 lines
2.1 KiB
C
81 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* This file is part of the coreboot project. */
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#include <AGESA.h>
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#include <northbridge/amd/agesa/state_machine.h>
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static const PCIe_PORT_DESCRIPTOR PortList[] = {
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3),
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PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 5,
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HotplugDisabled,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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AspmL0sL1,
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0x01,
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0)
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},
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/* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2),
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PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 4,
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HotplugDisabled,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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AspmL0sL1,
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0x02,
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0)
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},
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/* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1),
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PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3,
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HotplugDisabled,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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AspmL0sL1,
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0x03,
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0)
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},
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/* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0),
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PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2,
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HotplugDisabled,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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AspmL0sL1,
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0x04,
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0)
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},
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/* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */
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{
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DESCRIPTOR_TERMINATE_LIST,
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PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
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PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1,
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HotplugDisabled,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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AspmL0sL1,
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0x05,
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0)
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}
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};
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static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
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.Flags = DESCRIPTOR_TERMINATE_LIST,
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.SocketId = 0,
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.PciePortList = PortList,
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.DdiLinkList = NULL,
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};
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void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
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{
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InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
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InitEarly->PlatformConfig.CStateMode = CStateModeC6;
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InitEarly->PlatformConfig.CpbMode = CpbModeAuto;
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}
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