Konstantin Aladyshev c2f2bd0a6d AGESA: Fix CR0_PE bit define ... AGESA code has wrong definition of CR0_PE bit (1 instead of 0). PE [Protected Mode Enable] is 0 bit in CR0 register (If PE=1, system is in protected mode, else system is in real mode) Bit 1 is MP [Monitor co-processor] (Controls interaction of WAIT/FWAIT instructions with TS flag in CR0) System uses CR0_PE define, but I didn't expect any consequences because of this bug. Change-Id: I54d9a8c0ee3af0a2e0267777036f227a9e05f3e1 Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru> Reviewed-on: http://review.coreboot.org/2591 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>		2013-03-08 07:30:06 +01:00
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amd	AGESA: Fix CR0_PE bit define	2013-03-08 07:30:06 +01:00
google	google/snow: enable GPIO entries and CHROMEOS in building	2013-02-25 18:50:00 +01:00
Kconfig	Add Google ChromeOS vendorcode directory	2012-03-30 01:59:38 +02:00
Makefile.inc	Add Google ChromeOS vendor support	2012-04-02 18:39:31 +02:00