Kyösti Mälkki 0e1ea279d0 AGESA vendorcode: Add ENABLE_MRC_CACHE option ... When selected, try to store and restore memory training results from/to SPI flash. This change only pulls in the required parts from vendorcode for the build. Change-Id: I12880237be494c71e1d4836abd2d4b714ba87762 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>		2017-10-05 13:23:27 +00:00
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allwinner	mb/*/*: Remove rtc nvram configurable baud rate	2017-09-23 11:06:25 +00:00
amd	AGESA vendorcode: Add ENABLE_MRC_CACHE option	2017-10-05 13:23:27 +00:00
armltd	vboot2: add verstage	2015-01-27 01:41:40 +01:00
dmp	src/cpu: add IS_ENABLED() around Kconfig symbol references	2017-07-13 23:55:25 +00:00
intel	chromeec: Remove checks for EC in RO	2017-10-04 20:55:12 +00:00
qemu-power8	cpu/qemu-power8: don't enable it for qemu-x86	2016-02-19 20:03:52 +01:00
qemu-x86	qemu-x86: Enable SMP support	2015-12-08 15:54:27 +01:00
ti	mb/*/*: Remove rtc nvram configurable baud rate	2017-09-23 11:06:25 +00:00
via	cpu/*: Add whitespace around '<<'	2017-06-28 00:23:32 +00:00
x86	cpu/x86: Align stack in SIPI handler	2017-10-02 16:15:42 +00:00
Kconfig	arch/x86: remove CAR global migration when postcar stage is used	2017-04-08 23:22:02 +02:00
Makefile.inc	Microcode: Show a useful warning when microcode bins are missing	2016-12-28 03:36:10 +01:00