c4eb45fa85
The chipset devicetree only has the essential PCIe devices enabled that are needed for the SoC code to work. It also defines aliases for all PCIe devices that can be used to reference the devices in the mainboard- specific devicetrees and devicetree overrides. To make the change easier to review that part will be done in a follow-up patch. Despite missing in the PPR, device pci 18.7 exists on Picasso. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6b7c3fd32579a23539594672593a243172c161c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
45 lines
1.2 KiB
Text
45 lines
1.2 KiB
Text
# SPDX-License-Identifier: GPL-2.0-or-later
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chip soc/amd/picasso
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# Start : OPN Performance Configuration
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# See devhub #55593 Chapter 3.2 for documentation
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# For the below fields, 0 indicates use SOC default
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# System config index
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register "system_config" = "2"
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# Set STAPM confiuration. All of these fields must be set >0 to take affect
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register "slow_ppt_limit_mW" = "25000"
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register "fast_ppt_limit_mW" = "30000"
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register "slow_ppt_time_constant_s" = "5"
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register "stapm_time_constant_s" = "200"
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register "sustained_power_limit_mW" = "15000"
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register "telemetry_vddcr_vdd_slope_mA" = "71222"
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register "telemetry_vddcr_vdd_offset" = "0"
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register "telemetry_vddcr_soc_slope_mA" = "28977"
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register "telemetry_vddcr_soc_offset" = "0"
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# End : OPN Performance Configuration
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# Enable I2C2 for trackpad, touchscreen, pen at 400kHz
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register "i2c[2]" = "{
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.speed = I2C_SPEED_FAST,
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}"
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# Enable I2C3 for H1 400kHz
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register "i2c[3]" = "{
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.speed = I2C_SPEED_FAST,
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.early_init = true,
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}"
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# See AMD 55570-B1 Table 13: PCI Device ID Assignments.
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device domain 0 on
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subsystemid 0x1022 0x1510 inherit
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device pci 1.7 on end # GPP Bridge 6 - NVME
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end # domain
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device mmio 0xfedc4000 on end
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end # chip soc/amd/picasso
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