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Aaron Durbin c5bb02f2ec soc/amd/common: fix SPI bar resource usage 
The ACPI code was not masking off the correct bits for publishing
the SPI bar to the OS.

It resulted in a dmesg messagelike:
	system 00:00: [mem 0xfec10002-0xfec11001] has been reserved
And /proc/iomem entry
	fec10002-fec11001 : pnp 00:00

These addresses are wrong because they are including bits of a
register that are not a part of the address.

Moreover, the code does not publish the eSPI register area either.
The eSPI registers live at 0x10000 added to the SPI bar. Lastly,
both regions are less than a page so only report a page of usage
for each.

Stoney Ridge's SPI bar register defines the address as 31:6 while
Picasso's SPI bar register defines the address as 31:8. Use Picasso's
valid mask for both cases because no one is assigning addresses
that are aligned to less than 256 bytes.

With the fixes, dmesg reports:
	system 00:00: [mem 0xfec10000-0xfec10fff] has been reserved
	system 00:00: [mem 0xfec20000-0xfec20fff] has been reserved
And /proc/iomem indicates:
	fec10000-fec10fff : pnp 00:00
	fec20000-fec20fff : pnp 00:00

BUG=b:160290629

Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I130b5ad26d9e13b44c25fbb35a05389f9e8841ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42959
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 		2020-07-02 15:55:46 +00:00
3rdparty 3rdparty/amd_blobs: Update Picasso PSP files 2020-07-01 05:21:31 +00:00
Documentation Documentation: Add several fixes 2020-07-01 21:51:26 +00:00
LICENSES drivers: Use SPDX identifiers 2020-05-25 22:19:21 +00:00
configs mb/ocp/deltalake: Add OCP Delta Lake mainboard 2020-06-22 12:21:18 +00:00
payloads libpayload/cbgfx: Fix overflow in transform_vector() 2020-06-28 21:52:18 +00:00
src soc/amd/common: fix SPI bar resource usage 2020-07-02 15:55:46 +00:00
tests tests/lib/Makefile.inc: remove a comment 2020-07-01 05:18:58 +00:00
util util/futility: Check for pkg-config and libcrypto 2020-07-01 18:12:05 +00:00
.checkpatch.conf
…
.clang-format
…
.editorconfig
…
.gitignore cbfstool: Build vboot library 2020-03-23 08:34:23 +00:00
.gitmodules Add qc_blobs repository 2020-06-30 08:57:03 +00:00
.gitreview
…
AUTHORS AUTHORS, util/: Drop individual copyright notices 2020-05-09 21:21:32 +00:00
COPYING
…
MAINTAINERS MAINTAINERS: Organize contents 2020-06-18 08:09:37 +00:00
Makefile Documentation: Add several fixes 2020-07-01 21:51:26 +00:00
Makefile.inc Add qc_blobs repository 2020-06-30 08:57:03 +00:00
README.md README.md: Remove link to deprecated wiki 2019-11-16 20:39:55 +00:00
gnat.adc treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
toolchain.inc Remove MAYBE_STATIC_BSS and ENV_STAGE_HAS_BSS_SECTION 2020-05-26 15:04:08 +00:00

README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of "unusual" things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that's worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • doxygen (for generating/viewing documentation)
  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

Copyright and License

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.