f3f2aa8a50
Change-Id: Ib78e746875e330e47540a6199343be62aa7e92a6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48830 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
56 lines
1.6 KiB
C
56 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <reg_script.h>
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#include <soc/device_nvs.h>
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#include <soc/iosf.h>
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#include <soc/pci_devs.h>
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#include <soc/ramstage.h>
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#include "chip.h"
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static const struct reg_script emmc_ops[] = {
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/* Enable 2ms card stable feature. */
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REG_PCI_OR32(0xa8, (1 << 24)),
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/* Enable HS200 */
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REG_PCI_WRITE32(0xa0, 0x446cc801),
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REG_PCI_WRITE32(0xa4, 0x80000807),
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/* cfio_regs_score_special_bits.sdio1_dummy_loopback_en=1 */
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REG_IOSF_OR(IOSF_PORT_SCORE, 0x49c0, (1 << 3)),
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/* CLKGATE_EN_1 . cr_scc_mipihsi_clkgate_en = 1 */
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REG_IOSF_RMW(IOSF_PORT_CCU, 0x1c, ~(3 << 26), (1 << 26)),
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/* Set slew for HS200 */
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REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c0, ~0x3c, 0x3c),
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REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c4, ~0x3c, 0x3c),
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/* Max timeout */
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REG_RES_WRITE8(PCI_BASE_ADDRESS_0, 0x002e, 0x0e),
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REG_SCRIPT_END,
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};
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static void emmc_init(struct device *dev)
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{
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struct soc_intel_baytrail_config *config = config_of(dev);
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printk(BIOS_DEBUG, "eMMC init\n");
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reg_script_run_on_dev(dev, emmc_ops);
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if (config->scc_acpi_mode)
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scc_enable_acpi_mode(dev, SCC_MMC_CTL, SCC_NVS_MMC);
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}
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static struct device_operations device_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = emmc_init,
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.ops_pci = &soc_pci_ops,
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};
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static const struct pci_driver southcluster __pci_driver = {
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.ops = &device_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = MMC45_DEVID,
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};
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