6b5bc77c9b
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
58 lines
1.7 KiB
C
58 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <console/console.h>
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#include <device/pci_ops.h>
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#include <device/pci_def.h>
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#include <cpu/x86/msr.h>
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#include <soc/pci_devs.h>
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#include <soc/northbridge.h>
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#include <soc/southbridge.h>
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#include <amdblocks/psp.h>
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void soc_enable_psp_early(void)
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{
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u32 base, limit;
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u16 cmd;
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/* Open a posted hole from 0x80000000 : 0xfed00000-1 */
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base = (0x80000000 >> 8) | MMIO_WE | MMIO_RE;
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limit = (ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8);
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pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_LIMIT0_LO, limit);
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pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_BASE0_LO, base);
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/* Preload a value into BAR and enable it */
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pci_write_config32(SOC_PSP_DEV, PSP_MAILBOX_BAR, PSP_MAILBOX_BAR3_BASE);
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pci_write_config32(SOC_PSP_DEV, PSP_BAR_ENABLES, PSP_MAILBOX_BAR_EN);
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/* Enable memory access and master */
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cmd = pci_read_config16(SOC_PSP_DEV, PCI_COMMAND);
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cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
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pci_write_config16(SOC_PSP_DEV, PCI_COMMAND, cmd);
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};
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void *soc_get_mbox_address(void)
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{
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uintptr_t psp_mmio;
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/* Check for presence of the PSP */
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if (pci_read_config32(SOC_PSP_DEV, PCI_VENDOR_ID) == 0xffffffff) {
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printk(BIOS_WARNING, "PSP: No SOC_PSP_DEV found at D%xF%x\n",
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PSP_DEV, PSP_FUNC);
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return 0;
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}
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/* Determine if Bar3Hide has been set, and if hidden get the base from
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* the MSR instead. */
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if (pci_read_config32(SOC_PSP_DEV, PSP_BAR_ENABLES) & BAR3HIDE) {
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psp_mmio = rdmsr(MSR_CU_CBBCFG).lo;
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if (psp_mmio == 0xffffffff) {
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printk(BIOS_WARNING, "PSP: BAR hidden, MSR val uninitialized\n");
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return 0;
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}
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} else {
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psp_mmio = pci_read_config32(SOC_PSP_DEV, PCI_BASE_ADDRESS_4) &
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~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
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}
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return (void *)(psp_mmio + PSP_MAILBOX_OFFSET);
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}
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