Furquan Shaikh 4b4c0c6016 northbridge/intel/sandybridge: Mask lower 20 bits of TOLUD and TOLM in hostbridge.asl ... Lower 20bits of TOLUD and TOLM registers include 19 reserved bits and 1 lock bit. If lock bit is set, then systemagent.asl would end up reporting the base address of low MMIO incorrectly i.e. off by 1. This change masks the lower 20 bits of TOLUD and TOM registers when exposing it in the ACPI tables to ensure that the base address of low MMIO region is reported correctly. Change-Id: Ib0ffd9a332fa9590de63f8828d30daa710fe50db Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41979 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>		2020-06-03 12:22:25 +00:00
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amd	src: Remove unused '#include <cpu/x86/lapic.h>'	2020-06-02 07:38:45 +00:00
intel	northbridge/intel/sandybridge: Mask lower 20 bits of TOLUD and TOLM in hostbridge.asl	2020-06-03 12:22:25 +00:00