coreboot-kgpe-d16/src/soc/intel/xeon_sp
Rocky Phagura c62c98a884 soc/intel/xeon_sp: Early programming of ACPI bar
ACPI bar was not programmed previously for which is needed to enable SMI's and
to check SMI status registers. The architecture of Lewisburg PCH is very
similar to SunrisePoint PCH thus we can use code from soc/intel/skylake.

TEST=build for Tiogapass and check ACPI base. Log message will now show
pmbase=501 (bit 0 is enable) instead of 0. Check by reading and writing
to io port 0x500.

Change-Id: If5a0c4daabf5c35dc2852434fe46712ac9b06379
Signed-off-by: Rocky Phagura <rphagura@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-06-02 07:37:08 +00:00
..
cpx soc/intel/xeon_sp/cpx: Remove redundant declaration 2020-05-28 09:29:01 +00:00
include/soc soc/intel/xeon_sp: Early programming of ACPI bar 2020-06-02 07:37:08 +00:00
skx soc/intel/xeon_sp/skx: Let iasl automatically resolve _PRT package size 2020-06-02 07:34:56 +00:00
bootblock.c soc/intel/xeon_sp: Early programming of ACPI bar 2020-06-02 07:37:08 +00:00
gpio.c treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
Kconfig soc/intel/xeon_sp: select UDK_2017_binding 2020-05-26 15:13:04 +00:00
lpc.c treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
Makefile.inc soc/intel/xeon_sp: Early programming of ACPI bar 2020-06-02 07:37:08 +00:00
pch.c soc/intel/xeon_sp: Early programming of ACPI bar 2020-06-02 07:37:08 +00:00
reset.c treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
romstage.c treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
spi.c treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
uncore.c treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
util.c treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00