cf45830982
This pin does not have a native function for eSPI. Nonetheless if we use eSPI, it should be configured as a GPIO and kept unconnected to allow S0ix entry. Also removed initialization of LPC pins in mainboard code as they are already initialized in chipset code. The settings fpr LPC pins in chipset code were updated to those that were previously in mainboard code and have been validated on LPC flavor of Geminilake RVP. BUG=b:79251613 BRANCH=none TEST=From kernel prompt in bip, type powerd_dbus_suspend. Check on EC console that SOC enters S0ix. Change-Id: Ie0c1013fee638a3b7a91469736efc0c25a1597fa Signed-off-by: Hannah Williams <hannah.williams@intel.com> Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/23742 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
107 lines
3.2 KiB
C
107 lines
3.2 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017-2018 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <intelblocks/lpc_lib.h>
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#include <intelblocks/rtc.h>
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#include <soc/gpio.h>
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#include <soc/pcr_ids.h>
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#include <soc/pm.h>
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#include "chip.h"
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static const struct lpc_mmio_range apl_lpc_fixed_mmio_ranges[] = {
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{ 0xfed40000, 0x8000 },
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{ 0xfedc0000, 0x4000 },
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{ 0xfed20800, 16 },
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{ 0xfed20880, 8 },
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{ 0xfed208e0, 16 },
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{ 0xfed208f0, 8 },
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{ 0xfed30800, 16 },
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{ 0xfed30880, 8 },
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{ 0xfed308e0, 16 },
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{ 0xfed308f0, 8 },
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{ 0, 0 }
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};
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const struct lpc_mmio_range *soc_get_fixed_mmio_ranges(void)
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{
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return apl_lpc_fixed_mmio_ranges;
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}
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static const struct pad_config lpc_gpios[] = {
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#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
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#if !IS_ENABLED(CONFIG_SOC_ESPI)
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PAD_CFG_NF(GPIO_147, UP_20K, DEEP, NF1), /* LPC_ILB_SERIRQ */
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PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_148, NONE, DEEP, NF1, HIZCRx1,
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DISPUPD), /* LPC_CLKOUT0 */
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PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_149, NONE, DEEP, NF1, HIZCRx1,
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DISPUPD), /* LPC_CLKOUT1 */
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PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_150, UP_20K, DEEP, NF1, HIZCRx1,
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DISPUPD), /* LPC_AD0 */
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PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_151, UP_20K, DEEP, NF1, HIZCRx1,
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DISPUPD), /* LPC_AD1 */
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PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_152, UP_20K, DEEP, NF1, HIZCRx1,
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DISPUPD), /* LPC_AD2 */
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PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_153, UP_20K, DEEP, NF1, HIZCRx1,
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DISPUPD), /* LPC_AD3 */
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PAD_CFG_NF(GPIO_154, UP_20K, DEEP, NF1), /* LPC_CLKRUNB */
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PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_155, UP_20K, DEEP, NF1, HIZCRx1,
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DISPUPD), /* LPC_FRAMEB */
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#else
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/*
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* LPC_CLKRUNB should be in GPIO mode for eSPI. Other pin settings
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* i.e. Rx path enable/disable, Tx path enable/disable, pull up
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* enable/disable etc are ignored. Leaving this pin in Native mode
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* will keep LPC Controller awake and prevent S0ix entry
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*/
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PAD_NC(GPIO_154, NONE),
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#endif /* !IS_ENABLED(CONFIG_SOC_ESPI) */
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#else
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PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1),
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PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1),
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PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1),
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PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1),
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PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1),
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PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1),
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PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1),
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PAD_CFG_NF(LPC_CLKOUT0, UP_20K, DEEP, NF1),
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PAD_CFG_NF(LPC_CLKOUT1, UP_20K, DEEP, NF1)
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#endif
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};
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void lpc_configure_pads(void)
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{
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gpio_configure_pads(lpc_gpios, ARRAY_SIZE(lpc_gpios));
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}
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void lpc_soc_init(struct device *dev)
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{
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const struct soc_intel_apollolake_config *cfg;
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cfg = dev->chip_info;
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if (!cfg) {
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printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
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return;
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}
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/* Set LPC Serial IRQ mode */
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lpc_set_serirq_mode(cfg->serirq_mode);
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/* Initialize RTC */
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rtc_init();
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}
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