99e578e3c1
This adds a file i82801gx/bootblock_gcc.c since other targets that don't yet C_ENVIRONMENT_BOOTBLOCK still use the romcc compiled bootblock.c. Tested on Foxconn D41S. Change-Id: I7e74838b0d5e9c192082084cfd9821996f0e4c50 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
44 lines
1.2 KiB
C
44 lines
1.2 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <device/pci_ops.h>
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#include <cpu/intel/car/bootblock.h>
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#include "i82801gx.h"
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static void enable_spi_prefetch(void)
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{
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u8 reg8;
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pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
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reg8 = pci_read_config8(dev, BIOS_CNTL);
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reg8 &= ~(3 << 2);
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reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
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pci_write_config8(dev, BIOS_CNTL, reg8);
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}
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void bootblock_early_southbridge_init(void)
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{
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enable_spi_prefetch();
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/* Enable RCBA */
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pci_devfn_t lpc_dev = PCI_DEV(0, 0x1f, 0);
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pci_write_config32(lpc_dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
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/* Enable upper 128bytes of CMOS */
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RCBA32(0x3400) = (1 << 2);
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/* Disable watchdog timer */
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RCBA32(GCS) = RCBA32(GCS) | 0x20;
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}
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