Furquan Shaikh 6d5e10c05d soc/intel/apollolake and mainboards: Use pcie_rp_clkreq_pin array ... This change uses an array pcie_rp_clkreq_pin for accepting CLKREQ# from mainboards instead of defining a separate property for each root port. This allows us to use memcpy to copy the entire array into FSP params as well as new properties for PCIe root ports can be added as arrays in future CLs. BUG=b:74633273 BRANCH=reef,coral Change-Id: Ifa05f1e38fcfd95063ec327712e472cdbd12dbb7 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>		2018-03-16 04:43:01 +00:00
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variants	soc/intel/apollolake and mainboards: Use pcie_rp_clkreq_pin array	2018-03-16 04:43:01 +00:00
acpi_tables.c
board_info.txt
bootblock.c	soc/intel/common/block: Add LPC Common code and use it for APL	2017-08-15 19:59:21 +00:00
chromeos.c	vboot: Assume EC_SOFTWARE_SYNC and VIRTUAL_DEV_SWITCH by default	2017-03-28 22:15:46 +02:00
chromeos.fmd	mainboard/google/reef: Add FPF_STATUS FMAP region	2017-03-15 03:42:55 +01:00
dsdt.asl
ec.c	mb/google/reef,sand: Set S0ix lazy wake mask	2018-01-23 17:27:28 +00:00
Kconfig	mb/google/*: Use newly added Chrome EC boardid function	2017-09-26 15:20:39 +00:00
Kconfig.name	mb/google: Add Chromebook marketing names	2017-11-17 21:33:25 +00:00
mainboard.c	mb/google/reef: provide override GPIO table in coral	2017-12-08 10:55:06 +00:00
Makefile.inc	mb/google/*: Use newly added Chrome EC boardid function	2017-09-26 15:20:39 +00:00
romstage.c
smihandler.c	mainboard/google/coral: power off EN_PP3300_DX_LTE_SOC when entering S5	2017-11-10 09:49:18 +00:00