660 lines
19 KiB
C
660 lines
19 KiB
C
/*
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* This file is part of the libpayload project.
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*
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* Copyright (C) 2008-2010 coresystems GmbH
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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//#define USB_DEBUG
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#include <arch/virtual.h>
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#include <usb/usb.h>
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#include "uhci.h"
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#include "uhci_private.h"
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static void uhci_start (hci_t *controller);
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static void uhci_stop (hci_t *controller);
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static void uhci_reset (hci_t *controller);
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static void uhci_shutdown (hci_t *controller);
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static int uhci_bulk (endpoint_t *ep, int size, u8 *data, int finalize);
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static int uhci_control (usbdev_t *dev, direction_t dir, int drlen, void *devreq,
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int dalen, u8 *data);
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static void* uhci_create_intr_queue (endpoint_t *ep, int reqsize, int reqcount, int reqtiming);
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static void uhci_destroy_intr_queue (endpoint_t *ep, void *queue);
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static u8* uhci_poll_intr_queue (void *queue);
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#if 0
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/* dump uhci */
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static void
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uhci_dump (hci_t *controller)
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{
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printf ("dump:\nUSBCMD: %x\n", uhci_reg_read16 (controller, USBCMD));
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printf ("USBSTS: %x\n", uhci_reg_read16 (controller, USBSTS));
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printf ("USBINTR: %x\n", uhci_reg_read16 (controller, USBINTR));
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printf ("FRNUM: %x\n", uhci_reg_read16 (controller, FRNUM));
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printf ("FLBASEADD: %x\n", uhci_reg_read32 (controller, FLBASEADD));
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printf ("SOFMOD: %x\n", uhci_reg_read8 (controller, SOFMOD));
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printf ("PORTSC1: %x\n", uhci_reg_read16 (controller, PORTSC1));
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printf ("PORTSC2: %x\n", uhci_reg_read16 (controller, PORTSC2));
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}
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#endif
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static void
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td_dump (td_t *td)
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{
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char td_value[3];
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const char *td_type;
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switch (td->pid) {
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case UHCI_SETUP:
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td_type="SETUP";
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break;
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case UHCI_IN:
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td_type="IN";
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break;
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case UHCI_OUT:
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td_type="OUT";
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break;
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default:
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sprintf(td_value, "%x", td->pid);
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td_type=td_value;
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}
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printf ("%s packet (at %lx) to %x.%x failed\n", td_type,
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virt_to_phys (td), td->dev_addr, td->endp);
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printf ("td (counter at %x) returns: ", td->counter);
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printf (" bitstuff err: %x, ", td->status_bitstuff_err);
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printf (" CRC err: %x, ", td->status_crc_err);
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printf (" NAK rcvd: %x, ", td->status_nakrcvd);
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printf (" Babble: %x, ", td->status_babble);
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printf (" Data Buffer err: %x, ", td->status_databuf_err);
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printf (" Stalled: %x, ", td->status_stalled);
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printf (" Active: %x\n", td->status_active);
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if (td->status_babble)
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printf (" Babble because of %s\n",
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td->status_bitstuff_err ? "host" : "device");
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if (td->status_active)
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printf (" still active - timeout?\n");
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}
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static void
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uhci_reset (hci_t *controller)
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{
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/* reset */
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uhci_reg_write16 (controller, USBCMD, 4);
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mdelay (50);
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uhci_reg_write16 (controller, USBCMD, 0);
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mdelay (10);
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uhci_reg_write16 (controller, USBCMD, 2);
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while ((uhci_reg_read16 (controller, USBCMD) & 2) != 0)
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mdelay (1);
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uhci_reg_write32 (controller, FLBASEADD,
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(u32) virt_to_phys (UHCI_INST (controller)->
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framelistptr));
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//printf ("framelist at %p\n",UHCI_INST(controller)->framelistptr);
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/* disable irqs */
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uhci_reg_write16 (controller, USBINTR, 0);
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/* reset framelist index */
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uhci_reg_write16 (controller, FRNUM, 0);
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uhci_reg_mask16 (controller, USBCMD, ~0, 0xc0); // max packets, configure flag
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uhci_start (controller);
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}
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hci_t *
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uhci_init (pcidev_t addr)
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{
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int i;
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u16 reg16;
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hci_t *controller = new_controller ();
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if (!controller)
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usb_fatal("Could not create USB controller instance.\n");
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controller->instance = malloc (sizeof (uhci_t));
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if(!controller->instance)
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usb_fatal("Not enough memory creating USB controller instance.\n");
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controller->start = uhci_start;
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controller->stop = uhci_stop;
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controller->reset = uhci_reset;
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controller->shutdown = uhci_shutdown;
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controller->bulk = uhci_bulk;
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controller->control = uhci_control;
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controller->create_intr_queue = uhci_create_intr_queue;
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controller->destroy_intr_queue = uhci_destroy_intr_queue;
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controller->poll_intr_queue = uhci_poll_intr_queue;
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for (i = 0; i < 128; i++) {
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controller->devices[i] = 0;
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}
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init_device_entry (controller, 0);
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UHCI_INST (controller)->roothub = controller->devices[0];
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controller->bus_address = addr;
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controller->reg_base = pci_read_config32 (controller->bus_address, 0x20) & ~1; /* ~1 clears the register type indicator that is set to 1 for IO space */
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/* kill legacy support handler */
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uhci_stop (controller);
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mdelay (1);
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uhci_reg_write16 (controller, USBSTS, 0x3f);
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reg16 = pci_read_config16(controller->bus_address, 0xc0);
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reg16 &= 0xdf80;
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pci_write_config16 (controller->bus_address, 0xc0, reg16);
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UHCI_INST (controller)->framelistptr = memalign (0x1000, 1024 * sizeof (flistp_t *)); /* 4kb aligned to 4kb */
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if (! UHCI_INST (controller)->framelistptr)
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usb_fatal("Not enough memory for USB frame list pointer.\n");
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memset (UHCI_INST (controller)->framelistptr, 0,
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1024 * sizeof (flistp_t));
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/* According to the *BSD UHCI code, this one is needed on some
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PIIX chips, because otherwise they misbehave. It must be
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added to the last chain.
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FIXME: this leaks, if the driver should ever be reinited
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for some reason. Not a problem now.
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*/
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td_t *antiberserk = memalign(16, sizeof(td_t));
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if (!antiberserk)
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usb_fatal("Not enough memory for chipset workaround.\n");
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memset(antiberserk, 0, sizeof(td_t));
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UHCI_INST (controller)->qh_prei = memalign (16, sizeof (qh_t));
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UHCI_INST (controller)->qh_intr = memalign (16, sizeof (qh_t));
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UHCI_INST (controller)->qh_data = memalign (16, sizeof (qh_t));
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UHCI_INST (controller)->qh_last = memalign (16, sizeof (qh_t));
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if (! UHCI_INST (controller)->qh_prei ||
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! UHCI_INST (controller)->qh_intr ||
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! UHCI_INST (controller)->qh_data ||
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! UHCI_INST (controller)->qh_last)
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usb_fatal ("Not enough memory for USB controller queues.\n");
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UHCI_INST (controller)->qh_prei->headlinkptr.ptr =
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virt_to_phys (UHCI_INST (controller)->qh_intr);
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UHCI_INST (controller)->qh_prei->headlinkptr.queue_head = 1;
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UHCI_INST (controller)->qh_prei->elementlinkptr.ptr = 0;
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UHCI_INST (controller)->qh_prei->elementlinkptr.terminate = 1;
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UHCI_INST (controller)->qh_intr->headlinkptr.ptr =
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virt_to_phys (UHCI_INST (controller)->qh_data);
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UHCI_INST (controller)->qh_intr->headlinkptr.queue_head = 1;
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UHCI_INST (controller)->qh_intr->elementlinkptr.ptr = 0;
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UHCI_INST (controller)->qh_intr->elementlinkptr.terminate = 1;
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UHCI_INST (controller)->qh_data->headlinkptr.ptr =
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virt_to_phys (UHCI_INST (controller)->qh_last);
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UHCI_INST (controller)->qh_data->headlinkptr.queue_head = 1;
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UHCI_INST (controller)->qh_data->elementlinkptr.ptr = 0;
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UHCI_INST (controller)->qh_data->elementlinkptr.terminate = 1;
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UHCI_INST (controller)->qh_last->headlinkptr.ptr = virt_to_phys (UHCI_INST (controller)->qh_data);
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UHCI_INST (controller)->qh_last->headlinkptr.terminate = 1;
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UHCI_INST (controller)->qh_last->elementlinkptr.ptr = virt_to_phys (antiberserk);
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UHCI_INST (controller)->qh_last->elementlinkptr.terminate = 1;
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for (i = 0; i < 1024; i++) {
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UHCI_INST (controller)->framelistptr[i].ptr =
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virt_to_phys (UHCI_INST (controller)->qh_prei);
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UHCI_INST (controller)->framelistptr[i].terminate = 0;
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UHCI_INST (controller)->framelistptr[i].queue_head = 1;
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}
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controller->devices[0]->controller = controller;
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controller->devices[0]->init = uhci_rh_init;
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controller->devices[0]->init (controller->devices[0]);
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uhci_reset (controller);
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return controller;
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}
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static void
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uhci_shutdown (hci_t *controller)
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{
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if (controller == 0)
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return;
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detach_controller (controller);
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UHCI_INST (controller)->roothub->destroy (UHCI_INST (controller)->
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roothub);
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uhci_reg_mask16 (controller, USBCMD, 0, 0); // stop work
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free (UHCI_INST (controller)->framelistptr);
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free (UHCI_INST (controller)->qh_prei);
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free (UHCI_INST (controller)->qh_intr);
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free (UHCI_INST (controller)->qh_data);
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free (UHCI_INST (controller)->qh_last);
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free (UHCI_INST (controller));
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free (controller);
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}
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static void
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uhci_start (hci_t *controller)
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{
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uhci_reg_mask16 (controller, USBCMD, ~0, 1); // start work on schedule
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}
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static void
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uhci_stop (hci_t *controller)
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{
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uhci_reg_mask16 (controller, USBCMD, ~1, 0); // stop work on schedule
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}
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#define GET_TD(x) ((void*)(((unsigned int)(x))&~0xf))
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static td_t *
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wait_for_completed_qh (hci_t *controller, qh_t *qh)
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{
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int timeout = 1000000; /* max 30 ms. */
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void *current = GET_TD (qh->elementlinkptr.ptr);
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while ((qh->elementlinkptr.terminate == 0) && (timeout-- > 0)) {
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if (current != GET_TD (qh->elementlinkptr.ptr)) {
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current = GET_TD (qh->elementlinkptr.ptr);
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timeout = 1000000;
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}
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uhci_reg_mask16 (controller, USBSTS, ~0, 0); // clear resettable registers
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udelay (30);
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}
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return (GET_TD (qh->elementlinkptr.ptr) ==
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0) ? 0 : GET_TD (phys_to_virt (qh->elementlinkptr.ptr));
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}
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static int
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maxlen (int size)
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{
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return (size - 1) & 0x7ff;
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}
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static int
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min (int a, int b)
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{
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if (a < b)
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return a;
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else
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return b;
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}
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static int
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uhci_control (usbdev_t *dev, direction_t dir, int drlen, void *devreq, int dalen,
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unsigned char *data)
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{
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int endp = 0; /* this is control: always 0 */
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int mlen = dev->endpoints[0].maxpacketsize;
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int count = (2 + (dalen + mlen - 1) / mlen);
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unsigned short req = ((unsigned short *) devreq)[0];
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int i;
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td_t *tds = memalign (16, sizeof (td_t) * count);
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memset (tds, 0, sizeof (td_t) * count);
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count--; /* to compensate for 0-indexed array */
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for (i = 0; i < count; i++) {
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tds[i].ptr = virt_to_phys (&tds[i + 1]);
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tds[i].depth_first = 1;
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tds[i].terminate = 0;
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}
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tds[count].ptr = 0;
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tds[count].depth_first = 1;
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tds[count].terminate = 1;
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tds[0].pid = UHCI_SETUP;
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tds[0].dev_addr = dev->address;
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tds[0].endp = endp;
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tds[0].maxlen = maxlen (drlen);
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tds[0].counter = 3;
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tds[0].data_toggle = 0;
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tds[0].lowspeed = dev->speed;
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tds[0].bufptr = virt_to_phys (devreq);
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tds[0].status_active = 1;
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int toggle = 1;
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for (i = 1; i < count; i++) {
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switch (dir) {
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case SETUP: tds[i].pid = UHCI_SETUP; break;
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case IN: tds[i].pid = UHCI_IN; break;
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case OUT: tds[i].pid = UHCI_OUT; break;
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}
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tds[i].dev_addr = dev->address;
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tds[i].endp = endp;
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tds[i].maxlen = maxlen (min (mlen, dalen));
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tds[i].counter = 3;
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tds[i].data_toggle = toggle;
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tds[i].lowspeed = dev->speed;
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tds[i].bufptr = virt_to_phys (data);
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tds[i].status_active = 1;
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toggle ^= 1;
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dalen -= mlen;
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data += mlen;
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}
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tds[count].pid = (dir == OUT) ? UHCI_IN : UHCI_OUT;
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tds[count].dev_addr = dev->address;
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tds[count].endp = endp;
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tds[count].maxlen = maxlen (0);
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tds[count].counter = 0; /* as per linux 2.4.10 */
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tds[count].data_toggle = 1;
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tds[count].lowspeed = dev->speed;
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tds[count].bufptr = 0;
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tds[count].status_active = 1;
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UHCI_INST (dev->controller)->qh_data->elementlinkptr.ptr =
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virt_to_phys (tds);
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UHCI_INST (dev->controller)->qh_data->elementlinkptr.queue_head = 0;
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UHCI_INST (dev->controller)->qh_data->elementlinkptr.terminate = 0;
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td_t *td = wait_for_completed_qh (dev->controller,
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UHCI_INST (dev->controller)->
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qh_data);
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int result;
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if (td == 0) {
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result = 0;
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} else {
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printf ("control packet, req %x\n", req);
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td_dump (td);
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result = 1;
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}
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free (tds);
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return result;
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}
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static td_t *
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create_schedule (int numpackets)
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{
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if (numpackets == 0)
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return 0;
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td_t *tds = memalign (16, sizeof (td_t) * numpackets);
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memset (tds, 0, sizeof (td_t) * numpackets);
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int i;
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for (i = 0; i < numpackets; i++) {
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tds[i].ptr = virt_to_phys (&tds[i + 1]);
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tds[i].terminate = 0;
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tds[i].queue_head = 0;
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tds[i].depth_first = 1;
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}
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tds[numpackets - 1].ptr = 0;
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tds[numpackets - 1].terminate = 1;
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tds[numpackets - 1].queue_head = 0;
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tds[numpackets - 1].depth_first = 0;
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return tds;
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}
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static void
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fill_schedule (td_t *td, endpoint_t *ep, int length, unsigned char *data,
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int *toggle)
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{
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switch (ep->direction) {
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case IN: td->pid = UHCI_IN; break;
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case OUT: td->pid = UHCI_OUT; break;
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case SETUP: td->pid = UHCI_SETUP; break;
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}
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td->dev_addr = ep->dev->address;
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td->endp = ep->endpoint & 0xf;
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td->maxlen = maxlen (length);
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if (ep->direction == SETUP)
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td->counter = 3;
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else
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td->counter = 0;
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td->data_toggle = *toggle & 1;
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td->lowspeed = ep->dev->speed;
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td->bufptr = virt_to_phys (data);
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td->status_active = 1;
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*toggle ^= 1;
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}
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static int
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run_schedule (usbdev_t *dev, td_t *td)
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{
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UHCI_INST (dev->controller)->qh_data->elementlinkptr.ptr =
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virt_to_phys (td);
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UHCI_INST (dev->controller)->qh_data->elementlinkptr.queue_head = 0;
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UHCI_INST (dev->controller)->qh_data->elementlinkptr.terminate = 0;
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td = wait_for_completed_qh (dev->controller,
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UHCI_INST (dev->controller)->qh_data);
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if (td == 0) {
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return 0;
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} else {
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td_dump (td);
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return 1;
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}
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}
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/* finalize == 1: if data is of packet aligned size, add a zero length packet */
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static int
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uhci_bulk (endpoint_t *ep, int size, u8 *data, int finalize)
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{
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int maxpsize = ep->maxpacketsize;
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if (maxpsize == 0)
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usb_fatal ("MaxPacketSize == 0!!!");
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int numpackets = (size + maxpsize - 1 + finalize) / maxpsize;
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if (numpackets == 0)
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return 0;
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td_t *tds = create_schedule (numpackets);
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|
int i = 0, toggle = ep->toggle;
|
|
while ((size > 0) || ((size == 0) && (finalize != 0))) {
|
|
fill_schedule (&tds[i], ep, min (size, maxpsize), data,
|
|
&toggle);
|
|
i++;
|
|
data += maxpsize;
|
|
size -= maxpsize;
|
|
}
|
|
if (run_schedule (ep->dev, tds) == 1) {
|
|
debug("Stalled. Trying to clean up.\n");
|
|
clear_stall (ep);
|
|
free (tds);
|
|
return 1;
|
|
}
|
|
ep->toggle = toggle;
|
|
free (tds);
|
|
return 0;
|
|
}
|
|
|
|
typedef struct {
|
|
qh_t *qh;
|
|
td_t *tds;
|
|
td_t *last_td;
|
|
u8 *data;
|
|
int lastread;
|
|
int total;
|
|
int reqsize;
|
|
} intr_q;
|
|
|
|
/* create and hook-up an intr queue into device schedule */
|
|
static void*
|
|
uhci_create_intr_queue (endpoint_t *ep, int reqsize, int reqcount, int reqtiming)
|
|
{
|
|
u8 *data = malloc(reqsize*reqcount);
|
|
td_t *tds = memalign(16, sizeof(td_t) * reqcount);
|
|
qh_t *qh = memalign(16, sizeof(qh_t));
|
|
|
|
if (!data || !tds || !qh)
|
|
usb_fatal ("Not enough memory to create USB intr queue prerequisites.\n");
|
|
|
|
qh->elementlinkptr.ptr = virt_to_phys(tds);
|
|
qh->elementlinkptr.queue_head = 0;
|
|
qh->elementlinkptr.terminate = 0;
|
|
|
|
intr_q *q = malloc(sizeof(intr_q));
|
|
if (!q)
|
|
usb_fatal ("Not enough memory to create USB intr queue.\n");
|
|
q->qh = qh;
|
|
q->tds = tds;
|
|
q->data = data;
|
|
q->lastread = 0;
|
|
q->total = reqcount;
|
|
q->reqsize = reqsize;
|
|
q->last_td = &tds[reqcount - 1];
|
|
|
|
memset (tds, 0, sizeof (td_t) * reqcount);
|
|
int i;
|
|
for (i = 0; i < reqcount; i++) {
|
|
tds[i].ptr = virt_to_phys (&tds[i + 1]);
|
|
tds[i].terminate = 0;
|
|
tds[i].queue_head = 0;
|
|
tds[i].depth_first = 0;
|
|
|
|
switch (ep->direction) {
|
|
case IN: tds[i].pid = UHCI_IN; break;
|
|
case OUT: tds[i].pid = UHCI_OUT; break;
|
|
case SETUP: tds[i].pid = UHCI_SETUP; break;
|
|
}
|
|
tds[i].dev_addr = ep->dev->address;
|
|
tds[i].endp = ep->endpoint & 0xf;
|
|
tds[i].maxlen = maxlen (reqsize);
|
|
tds[i].counter = 0;
|
|
tds[i].data_toggle = ep->toggle & 1;
|
|
tds[i].lowspeed = ep->dev->speed;
|
|
tds[i].bufptr = virt_to_phys (data);
|
|
tds[i].status_active = 1;
|
|
ep->toggle ^= 1;
|
|
data += reqsize;
|
|
}
|
|
tds[reqcount - 1].ptr = 0;
|
|
tds[reqcount - 1].terminate = 1;
|
|
tds[reqcount - 1].queue_head = 0;
|
|
tds[reqcount - 1].depth_first = 0;
|
|
for (i = reqtiming; i < 1024; i += reqtiming) {
|
|
/* FIXME: wrap in another qh, one for each occurance of the qh in the framelist */
|
|
qh->headlinkptr.ptr = UHCI_INST (ep->dev->controller)->framelistptr[i].ptr;
|
|
qh->headlinkptr.terminate = 0;
|
|
UHCI_INST (ep->dev->controller)->framelistptr[i].ptr = virt_to_phys(qh);
|
|
UHCI_INST (ep->dev->controller)->framelistptr[i].terminate = 0;
|
|
UHCI_INST (ep->dev->controller)->framelistptr[i].queue_head = 1;
|
|
}
|
|
return q;
|
|
}
|
|
|
|
/* remove queue from device schedule, dropping all data that came in */
|
|
static void
|
|
uhci_destroy_intr_queue (endpoint_t *ep, void *q_)
|
|
{
|
|
intr_q *q = (intr_q*)q_;
|
|
u32 val = virt_to_phys (q->qh);
|
|
u32 end = virt_to_phys (UHCI_INST (ep->dev->controller)->qh_intr);
|
|
int i;
|
|
for (i=0; i<1024; i++) {
|
|
u32 oldptr = 0;
|
|
u32 ptr = UHCI_INST (ep->dev->controller)->framelistptr[i].ptr;
|
|
while (ptr != end) {
|
|
if (((qh_t*)phys_to_virt(ptr))->elementlinkptr.ptr == val) {
|
|
((qh_t*)phys_to_virt(oldptr))->headlinkptr.ptr = ((qh_t*)phys_to_virt(ptr))->headlinkptr.ptr;
|
|
free(phys_to_virt(ptr));
|
|
break;
|
|
}
|
|
oldptr = ptr;
|
|
ptr = ((qh_t*)phys_to_virt(ptr))->headlinkptr.ptr;
|
|
}
|
|
}
|
|
free(q->data);
|
|
free(q->tds);
|
|
free(q->qh);
|
|
free(q);
|
|
}
|
|
|
|
/* read one intr-packet from queue, if available. extend the queue for new input.
|
|
return NULL if nothing new available.
|
|
Recommended use: while (data=poll_intr_queue(q)) process(data);
|
|
*/
|
|
static u8*
|
|
uhci_poll_intr_queue (void *q_)
|
|
{
|
|
intr_q *q = (intr_q*)q_;
|
|
if (q->tds[q->lastread].status_active == 0) {
|
|
/* FIXME: handle errors */
|
|
int current = q->lastread;
|
|
int previous;
|
|
if (q->lastread == 0) {
|
|
previous = q->total - 1;
|
|
} else {
|
|
previous = q->lastread - 1;
|
|
}
|
|
q->tds[previous].status = 0;
|
|
q->tds[previous].ptr = 0;
|
|
q->tds[previous].terminate = 1;
|
|
if (q->last_td != &q->tds[previous]) {
|
|
q->last_td->ptr = virt_to_phys(&q->tds[previous]);
|
|
q->last_td->terminate = 0;
|
|
q->last_td = &q->tds[previous];
|
|
}
|
|
q->tds[previous].status_active = 1;
|
|
q->lastread = (q->lastread + 1) % q->total;
|
|
return &q->data[current*q->reqsize];
|
|
}
|
|
return NULL;
|
|
}
|
|
|
|
void
|
|
uhci_reg_write32 (hci_t *ctrl, usbreg reg, u32 value)
|
|
{
|
|
outl (value, ctrl->reg_base + reg);
|
|
}
|
|
|
|
u32
|
|
uhci_reg_read32 (hci_t *ctrl, usbreg reg)
|
|
{
|
|
return inl (ctrl->reg_base + reg);
|
|
}
|
|
|
|
void
|
|
uhci_reg_write16 (hci_t *ctrl, usbreg reg, u16 value)
|
|
{
|
|
outw (value, ctrl->reg_base + reg);
|
|
}
|
|
|
|
u16
|
|
uhci_reg_read16 (hci_t *ctrl, usbreg reg)
|
|
{
|
|
return inw (ctrl->reg_base + reg);
|
|
}
|
|
|
|
void
|
|
uhci_reg_write8 (hci_t *ctrl, usbreg reg, u8 value)
|
|
{
|
|
outb (value, ctrl->reg_base + reg);
|
|
}
|
|
|
|
u8
|
|
uhci_reg_read8 (hci_t *ctrl, usbreg reg)
|
|
{
|
|
return inb (ctrl->reg_base + reg);
|
|
}
|
|
|
|
void
|
|
uhci_reg_mask32 (hci_t *ctrl, usbreg reg, u32 andmask, u32 ormask)
|
|
{
|
|
uhci_reg_write32 (ctrl, reg,
|
|
(uhci_reg_read32 (ctrl, reg) & andmask) | ormask);
|
|
}
|
|
|
|
void
|
|
uhci_reg_mask16 (hci_t *ctrl, usbreg reg, u16 andmask, u16 ormask)
|
|
{
|
|
uhci_reg_write16 (ctrl, reg,
|
|
(uhci_reg_read16 (ctrl, reg) & andmask) | ormask);
|
|
}
|
|
|
|
void
|
|
uhci_reg_mask8 (hci_t *ctrl, usbreg reg, u8 andmask, u8 ormask)
|
|
{
|
|
uhci_reg_write8 (ctrl, reg,
|
|
(uhci_reg_read8 (ctrl, reg) & andmask) | ormask);
|
|
}
|