109 lines
3.8 KiB
C
109 lines
3.8 KiB
C
/*
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* This file is part of the libpayload project.
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*
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* Copyright (C) 2010 coresystems GmbH
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _PCI_PCI_H
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#define _PCI_PCI_H
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/* we implement at least this version */
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#define PCI_LIB_VERSION 0x020200
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#include <pci.h>
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#define PCI_CLASS_DEVICE REG_CLASS_DEV
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#define PCI_SUBSYSTEM_VENDOR_ID REG_SUBSYS_VENDOR_ID
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#define PCI_SUBSYSTEM_ID REG_SUBSYS_ID
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#define PCI_COMMAND REG_COMMAND
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#define PCI_COMMAND_IO REG_COMMAND_IO
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#define PCI_COMMAND_MEMORY REG_COMMAND_MEM
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#define PCI_COMMAND_MASTER REG_COMMAND_BM
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#define PCI_HEADER_TYPE REG_HEADER_TYPE
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#define PCI_HEADER_TYPE_NORMAL HEADER_TYPE_NORMAL
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#define PCI_HEADER_TYPE_BRIDGE HEADER_TYPE_BRIDGE
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#define PCI_HEADER_TYPE_CARDBUS HEADER_TYPE_CARDBUS
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#define PCI_BASE_ADDRESS_0 0x10
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#define PCI_BASE_ADDRESS_1 0x14
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#define PCI_BASE_ADDRESS_2 0x18
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#define PCI_BASE_ADDRESS_3 0x1c
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#define PCI_BASE_ADDRESS_4 0x20
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#define PCI_BASE_ADDRESS_5 0x24
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#define PCI_BASE_ADDRESS_SPACE 1 // mask
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#define PCI_BASE_ADDRESS_SPACE_IO 1
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#define PCI_BASE_ADDRESS_SPACE_MEM 0
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#define PCI_BASE_ADDRESS_IO_MASK ~0xf
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#define PCI_BASE_ADDRESS_MEM_MASK ~0x3
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#define PCI_ROM_ADDRESS 0x30
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#define PCI_ROM_ADDRESS1 0x38 // on bridges
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#define PCI_ROM_ADDRESS_MASK ~0x7ff
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#define PCI_VENDOR_ID_INTEL 0x8086
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struct pci_dev {
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u16 domain;
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u8 bus, dev, func;
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u16 vendor_id, device_id;
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struct pci_dev *next;
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};
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/*
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* values to match devices against.
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* "-1" means "don't care", everything else requires an exact match
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*/
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struct pci_filter {
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int domain, bus, dev, func;
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int vendor, device;
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struct pci_dev *devices;
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};
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struct pci_access {
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struct pci_dev *devices;
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};
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u8 pci_read_byte(struct pci_dev *dev, int pos);
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u16 pci_read_word(struct pci_dev *dev, int pos);
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u32 pci_read_long(struct pci_dev *dev, int pos);
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int pci_write_byte(struct pci_dev *dev, int pos, u8 data);
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int pci_write_word(struct pci_dev *dev, int pos, u16 data);
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int pci_write_long(struct pci_dev *dev, int pos, u32 data);
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struct pci_access *pci_alloc(void);
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void pci_init(struct pci_access*);
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void pci_cleanup(struct pci_access*);
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char *pci_filter_parse_slot(struct pci_filter*, const char*);
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int pci_filter_match(struct pci_filter*, struct pci_dev*);
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void pci_filter_init(struct pci_access*, struct pci_filter*);
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void pci_scan_bus(struct pci_access*);
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struct pci_dev *pci_get_dev(struct pci_access*, u16, u8, u8, u8);
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#endif
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