Sooi, Li Cheng c76e9982b2 soc/intel/skylake: Add CPU, PCH, MCH, IGD, XHCI and UART IDs for SKL/KBL HALO SOC ... Add CPU, PCH, MCH, IGD, XHCI and UART IDs for SKL/KBL HALO SOC Change-Id: I6a44d55d1588d2620bd1179ea7dc327922f49fd7 Signed-off-by: Sooi, Li Cheng <li.cheng.sooi@intel.com> Reviewed-on: https://review.coreboot.org/18028 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)		2017-02-16 05:09:13 +01:00
..
acpi
arch	src/Kconfig: Move bootblock behavior to arch/x86 as TODO suggested	2017-02-14 19:03:42 +01:00
commonlib	buildsystem: Drop explicit (k)config.h includes	2016-12-08 19:46:53 +01:00
console	console: Enable do_printk_va_list for VBOOT	2016-12-27 18:07:39 +01:00
cpu	cpu/intel/model_6fx: Add Conroe-L to cpu_device_id list	2017-01-10 19:54:12 +01:00
device	ddr3 spd: move accessor code into lib/spd_bin.c	2017-02-10 18:04:33 +01:00
drivers	drivers/pc80/tpm: Update default acpi path	2017-02-14 18:59:30 +01:00
ec	ec/google/chromeec: let platform prepare for reboot when resetting EC	2017-02-07 17:45:05 +01:00
include	ddr3 spd: move accessor code into lib/spd_bin.c	2017-02-10 18:04:33 +01:00
lib	ddr3 spd: move accessor code into lib/spd_bin.c	2017-02-10 18:04:33 +01:00
mainboard	siemens/mc_apl1: Make basic settings for booting the mainboard	2017-02-15 21:38:03 +01:00
northbridge	nb/i945/gma.c: Remove writes to FIFO Watermark registers	2017-02-14 13:03:02 +01:00
soc	soc/intel/skylake: Add CPU, PCH, MCH, IGD, XHCI and UART IDs for SKL/KBL HALO SOC	2017-02-16 05:09:13 +01:00
southbridge	southbridge/intel/common/firmware: allow locking ME without HAVE_ME_BIN	2017-02-08 15:12:50 +01:00
superio	sio/ite/it8783ef: Return (0) in ACPI _PSC methods	2016-12-13 22:49:24 +01:00
vboot	build system: mark sub-make invocations as parallelizable	2017-01-31 18:51:55 +01:00
vendorcode	AGESA: Remove nonexistent include path	2017-02-14 10:57:45 +01:00
Kconfig	src/Kconfig: Move bootblock behavior to arch/x86 as TODO suggested	2017-02-14 19:03:42 +01:00