c7757f20ac
models 6ex and 6fx (core and core2 solo and duo). Also, use the names suggested by Intel for the microcode files instead our short version of it. This allows to create new microcode patches with a simple set of scripts. * some minor cpu setup fixes for c and p states Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4235 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
32 lines
719 B
Text
32 lines
719 B
Text
# This will make a target directory of ./VENDOR_MAINBOARD
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target VENDOR_MAINBOARD
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mainboard VENDOR/MAINBOARD
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option CC="CROSSCC"
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option CROSS_COMPILE="CROSS_PREFIX"
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option HOSTCC="CROSS_HOSTCC"
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__COMPRESSION__
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__LOGLEVEL__
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option ROM_SIZE=1024*1024
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option FALLBACK_SIZE=1024*512
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romimage "normal"
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option USE_FALLBACK_IMAGE=0
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option ROM_IMAGE_SIZE=0x24000
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option COREBOOT_EXTRA_VERSION=".0-normal"
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payload __PAYLOAD__
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end
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romimage "fallback"
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option USE_FALLBACK_IMAGE=1
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option ROM_IMAGE_SIZE=0x24000
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option COREBOOT_EXTRA_VERSION=".0-fallback"
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payload __PAYLOAD__
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end
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buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
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#pci_rom ../../../misc/kontron-pci8086,27a2.rom vendor_id=0x8086 device_id=0x27a2
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