5b1d51ba2e
This patch tries to improve the pcie portA configuration. The Matrox G550e PCIe gfx card shipped along with the dev board is supported. Signed-off-by: Arnaud Maye <arnaud.maye@4dsp.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4615 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
40 lines
1.4 KiB
Text
40 lines
1.4 KiB
Text
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2008 Arastra, Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License version 2 as
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## published by the Free Software Foundation.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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target truxton
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mainboard intel/truxton
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## CONFIG_ROM_SIZE is the total number of bytes allocated for coreboot use
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## (normal AND fallback images and payloads).
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option CONFIG_ROM_SIZE = 2 * 1024 * 1024
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## CONFIG_ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image,
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## not including any payload.
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option CONFIG_ROM_IMAGE_SIZE = 128 * 1024
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## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image
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## (including payload) will use
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option CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
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romimage "fallback"
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option CONFIG_USE_FALLBACK_IMAGE=1
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payload /tmp/seabios.elf
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end
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buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
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