a9b44f4c79
In pursuit of the goal of eliminating the proliferation of raw region devices to represent CBFS files outside of the CBFS core code, this patch removes the get_spd_cbfs_rdev() API and instead replaces it with spd_cbfs_map() which will find and map the SPD file in one go and return a pointer to the relevant section. (This makes it impossible to unmap the mapping again, which all but one of the users didn't bother to do anyway since the API is only used on platforms with memory-mapped flash. Presumably this will stay that way in the future so this is not something worth worrying about.) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Iec7571bec809f2f0712e7a97b4c853b8b40702d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
60 lines
1.7 KiB
C
60 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef SPD_BIN_H
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#define SPD_BIN_H
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#include <stdint.h>
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#include <commonlib/region.h>
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#define SPD_PAGE_LEN 256
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#define SPD_PAGE_LEN_DDR4 512
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#define SPD_PAGE_0 (0x6C >> 1)
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#define SPD_PAGE_1 (0x6E >> 1)
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#define SPD_DRAM_TYPE 2
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#define SPD_DRAM_DDR3 0x0B
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#define SPD_DRAM_LPDDR3_INTEL 0xF1
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#define SPD_DRAM_LPDDR3_JEDEC 0x0F
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#define SPD_DRAM_DDR4 0x0C
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#define SPD_DRAM_LPDDR4 0x10
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#define SPD_DRAM_LPDDR4X 0x11
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#define SPD_DRAM_DDR5 0x12
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#define SPD_DRAM_LPDDR5 0x13
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#define SPD_DENSITY_BANKS 4
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#define SPD_ADDRESSING 5
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#define SPD_SN_LEN 4
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#define DDR3_ORGANIZATION 7
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#define DDR3_BUS_DEV_WIDTH 8
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#define DDR4_ORGANIZATION 12
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#define DDR4_BUS_DEV_WIDTH 13
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#define DDR3_SPD_PART_OFF 128
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#define DDR3_SPD_PART_LEN 18
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#define DDR3_SPD_SN_OFF 122
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#define LPDDR3_SPD_PART_OFF 128
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#define LPDDR3_SPD_PART_LEN 18
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#define DDR4_SPD_PART_OFF 329
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#define DDR4_SPD_PART_LEN 20
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#define DDR4_SPD_SN_OFF 325
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struct spd_block {
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u8 addr_map[CONFIG_DIMM_MAX]; /* 7 bit I2C addresses */
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u8 *spd_array[CONFIG_DIMM_MAX];
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/* Length of each dimm */
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u16 len;
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};
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void print_spd_info(uint8_t spd[]);
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uintptr_t spd_cbfs_map(u8 spd_index);
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void dump_spd_info(struct spd_block *blk);
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void get_spd_smbus(struct spd_block *blk);
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/*
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* get_spd_sn returns the SODIMM serial number. It only supports DDR3 and DDR4.
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* return CB_SUCCESS, sn is the serial number and sn=0xffffffff if the dimm is not present.
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* return CB_ERR, if dram_type is not supported or addr is a zero.
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*/
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enum cb_err get_spd_sn(u8 addr, u32 *sn);
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/* expects SPD size to be 128 bytes, reads from "spd.bin" in CBFS and
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verifies the checksum. Only available if CONFIG_DIMM_SPD_SIZE == 128. */
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int read_ddr3_spd_from_cbfs(u8 *buf, int idx);
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#endif
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