coreboot-kgpe-d16/src/soc
Duncan Laurie c99681f4f2 broadwell: Clean up ME device and add new ME10 flow
In order to avoid a 300ms timeout waiting for mbp_cleared flag
to be set there is a new flow for the ME10 1.5MB firwmare that
we can follow which will save significant boot time.

This requires sending new commands that do not generate an ACK
message, and ensuring an HMRFPO LOCK message is sent.

In addition now that the delay is removed clean up the ME path
to do the work in init() step and add a final() step that does
the disabling of the PCI device.

BUG=chrome-os-partner:30637,chrome-os-partner:34134
BRANCH=samus,auron
TEST=build and boot on samus, measure ~300ms speedup in boot time

Original-Change-Id: I753087ecd65f6ebed9f812318a359f893e01da9f
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/234400
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 25aff4b188dc94a99af30869a162e01e3fa8dee7)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ia35373548a902a718155a1a57057f55067d2f3ac
Reviewed-on: http://review.coreboot.org/9697
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-15 21:45:40 +02:00
..
imgtec pistachio: implement clock setup for I2C0 2015-04-14 12:08:44 +02:00
intel broadwell: Clean up ME device and add new ME10 flow 2015-04-15 21:45:40 +02:00
marvell CBFS: Automate ROM image layout and remove hardcoded offsets 2015-04-14 09:01:27 +02:00
nvidia tegra132: lock down VPR 2015-04-14 12:07:39 +02:00
qualcomm CBFS: Automate ROM image layout and remove hardcoded offsets 2015-04-14 09:01:27 +02:00
rockchip rk3288: send correct EDID buffer size 2015-04-15 16:48:24 +02:00
samsung timer: Reestablish init_timer(), consolidate timer initialization calls 2015-04-14 09:03:28 +02:00
ucb kconfig: drop intermittend forwarder files 2015-04-07 17:40:28 +02:00
Makefile.inc cosmos: add template for soc and board files 2015-04-09 00:21:21 +02:00