Martin Roth c9ce5f6ec8 soc/amd/mendocino: Mark PCIe GPP bridges as hidden instead of off ... When one of the General-Purpose PCIe bridges is not used, it doesn't show up on the PCI bus at all, so coreboot notes it as an issue in the devicetree. This happens even if the device is marked as off. To solve this, we're marking the GPP bridge devices in devicetree as hidden, so they'll only show up in devicetree if they're actually used on a mainboard. BUG=None TEST=Don't see the "PCI: Leftover static devices:" warning for these in the boot console. BRANCH=skyrim Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I517776e4dedc70e957a0c836ab3c2e5d49e156d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74526 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>		2023-04-21 15:25:41 +00:00
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amd	soc/amd/mendocino: Mark PCIe GPP bridges as hidden instead of off	2023-04-21 15:25:41 +00:00
cavium	treewide: Remove duplicated include <device/pci.h>	2023-02-01 03:03:34 +00:00
example/min86	soc: Add SPDX license headers to Makefiles	2022-10-31 03:27:13 +00:00
intel	soc/intel/meteorlake: Add VPU into the DMAR SATC table	2023-04-21 15:23:49 +00:00
mediatek	soc/mediatek: Add assert for regulator VRF12	2023-04-14 12:09:24 +00:00
nvidia	treewide: stop calling custom TPM log "TCPA"	2023-01-11 16:00:55 +00:00
qualcomm	qualcomm/common: Pass FMAX_LIMIT flag for Lazor board to QcLib	2023-03-17 00:34:08 +00:00
rockchip	cbmem_top_chipset: Change the return value to uintptr_t	2022-11-18 16:00:45 +00:00
samsung	treewide: Fix old-style declarations	2023-01-17 04:23:49 +00:00
sifive/fu540	cbmem_top_chipset: Change the return value to uintptr_t	2022-11-18 16:00:45 +00:00
ti	src/soc/ti: Remove unnecessary space after casts	2022-11-22 13:42:28 +00:00
ucb/riscv	cbmem_top_chipset: Change the return value to uintptr_t	2022-11-18 16:00:45 +00:00