ca436cb247
tegra124: Add a test function which spams exclamation points on the UART. This function spews characters on the console and, until we have a working console, is an easy way to see whether the system boots to a particular point. For some reason waiting for transmitter to be empty hangs, but transmitting characters still works. Old-Change-Id: I1622c8a58849f4b8bdcaa67500b81042d7346df4 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171030 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit e0059181958cfe8afec2f3a7ea732e81f5d55e5d) tegra124: Re-enable waiting for the transmitter to empty in the test function. The compiler was emitting code compatible with armv7-a, but the bootblock was running on a core which uses armv4t. By coincidence, it was emitting an instruction which is unavailable on armv4t when checking the value of the UART's LSR register. Now that the bootblock is compiled with more appropriate flags, this code can be re-introduced. Old-Change-Id: I7ecada4138b0889b963d1a8b19a4bab8e0bb1add Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/170997 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 2a0adceb5029c8ee633d17c82dbb11e48d30349d) tegra124: Seperate out the non-UART specific hardcoded init in the bootblock. The hardcoded init in the test function in the bootblock is actually useful generally because it doesn't belong in the UART driver itself but is necessary for the UART to work. Until we have real implementations for the pinmux, etc., we can use that code to get the UART and console going. Old-Change-Id: I2efe0b571d8b022eb2a2e5569620558540b28373 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171334 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit ae7d4d890be1936cc86dc15adeb33f3b46a51ae5) tegra124: Implement and enable serial console support for tegra124. The driver is very similar to the 8250 driver, except it isn't in two parts, and it also spaces its registers 4 bytes apart instead of having them directly adjacent to each other. Also, eliminate the UART test function in the bootblock. It's no longer needed since the actual console output serves the same purpose. Right now the clock divisor is fixed for now, and we'll want to actually figure out what value to use at some point. Old-Change-Id: Idd659222901eb76b0ed8cbb986deb5124096f2f6 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171337 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 86f5e2875b18901b349283cfbcd4f8cc88b7a019) Squashed 4 commits related to uart support for tegra124. Modified the new uart.c to look like the uart.c for exynos5420. Change-Id: I490cba014a43d58c30c48ca9ddcae2b00095b7a6 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6764 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> |
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| 3rdparty@45f0c04fd7 | ||
| documentation | ||
| payloads | ||
| src | ||
| util | ||
| .gitignore | ||
| .gitmodules | ||
| .gitreview | ||
| COPYING | ||
| Makefile | ||
| Makefile.inc | ||
| README | ||
| toolchain.inc | ||
README
------------------------------------------------------------------------------- coreboot README ------------------------------------------------------------------------------- coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload. With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required. coreboot was formerly known as LinuxBIOS. Payloads -------- After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot. See http://www.coreboot.org/Payloads for a list of supported payloads. Supported Hardware ------------------ coreboot supports a wide range of chipsets, devices, and mainboards. For details please consult: * http://www.coreboot.org/Supported_Motherboards * http://www.coreboot.org/Supported_Chipsets_and_Devices Build Requirements ------------------ * gcc / g++ * make Optional: * doxygen (for generating/viewing documentation) * iasl (for targets with ACPI support) * gdb (for better debugging facilities on some targets) * ncurses (for 'make menuconfig') * flex and bison (for regenerating parsers) Building coreboot ----------------- Please consult http://www.coreboot.org/Build_HOWTO for details. Testing coreboot Without Modifying Your Hardware ------------------------------------------------ If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU. Please see http://www.coreboot.org/QEMU for details. Website and Mailing List ------------------------ Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website: http://www.coreboot.org You can contact us directly on the coreboot mailing list: http://www.coreboot.org/Mailinglist Copyright and License --------------------- The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details. coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details. This makes the resulting coreboot images licensed under the GPL, version 2.