0dbea48d46
I2C driver is replicated in each generation of AMD SoCs. Introduce a
common I2C driver that can be used across all the AMD SoCs. To begin
with, peripheral reset functionality is moved into this common driver.
SoC specific I2C driver passes the SCL pin configuration in order for
the common driver to reset the peripherals. More functionality can be
moved here in subsequent changes.
Also sb_reset_i2c_slaves() is renamed as sb_reset_i2c_peripherals() as
an effort towards using inclusive language.
BUG=None
TEST=Build Dalboz and Grunt. Boot to OS in Dalboz. Ensure that the I2C
peripherals are detected as earlier in Dalboz.
localhost ~ # i2cdetect -y 0
Warning: Can't use SMBus Quick Write command, will skip some addresses
0 1 2 3 4 5 6 7 8 9 a b c d e f
00:
10:
20:
30: -- -- -- -- -- -- -- --
40:
50: 50 51 -- -- -- -- -- -- 58 59 -- -- -- -- -- --
60:
70:
localhost ~ # i2cdetect -y 1
Warning: Can't use SMBus Quick Write command, will skip some addresses
0 1 2 3 4 5 6 7 8 9 a b c d e f
00:
10:
20:
30: -- -- -- -- -- -- -- --
40:
50: UU -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
60:
70:
Change-Id: I9f735dcfe8375abdc88ff06e8c4f8a6b741bc085
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Suggested-by: Kyosti Malkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
80 lines
1.9 KiB
C
80 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <amdblocks/acpimmio.h>
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#include <amdblocks/espi.h>
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#include <amdblocks/i2c.h>
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#include <amdblocks/lpc.h>
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#include <amdblocks/smbus.h>
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#include <amdblocks/spi.h>
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#include <console/console.h>
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#include <soc/i2c.h>
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#include <soc/southbridge.h>
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#include <soc/uart.h>
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#include <types.h>
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#include "chip.h"
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/* This table is for the initial conversion of all SCL pins to input with no pull. */
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static const struct soc_i2c_scl_pin i2c_scl_pins[] = {
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{ PAD_GPI(I2C2_SCL_PIN, PULL_NONE), GPIO_I2C2_SCL },
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{ PAD_GPI(I2C3_SCL_PIN, PULL_NONE), GPIO_I2C3_SCL },
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/* I2C4 is a peripheral device only */
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};
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static void lpc_configure_decodes(void)
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{
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if (CONFIG(POST_IO) && (CONFIG_POST_IO_PORT == 0x80))
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lpc_enable_port80();
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}
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static void reset_i2c_peripherals(void)
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{
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const struct soc_amd_picasso_config *cfg = config_of_soc();
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struct soc_i2c_peripheral_reset_info reset_info;
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reset_info.i2c_scl_reset_mask = cfg->i2c_scl_reset & GPIO_I2C_MASK;
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reset_info.i2c_scl = i2c_scl_pins;
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reset_info.num_pins = ARRAY_SIZE(i2c_scl_pins);
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sb_reset_i2c_peripherals(&reset_info);
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}
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/* Before console init */
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void fch_pre_init(void)
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{
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lpc_early_init();
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if (!CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI))
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lpc_configure_decodes();
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fch_spi_early_init();
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enable_acpimmio_decode_pm04();
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fch_smbus_init();
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fch_enable_cf9_io();
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fch_enable_legacy_io();
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enable_aoac_devices();
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reset_i2c_peripherals();
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/*
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* On reset Range_0 defaults to enabled. We want to start with a clean
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* slate to not have things unexpectedly enabled.
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*/
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clear_uart_legacy_config();
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if (CONFIG(AMD_SOC_CONSOLE_UART))
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set_uart_config(CONFIG_UART_FOR_CONSOLE);
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}
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/* After console init */
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void fch_early_init(void)
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{
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fch_print_pmxc0_status();
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i2c_soc_early_init();
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if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING))
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lpc_disable_spi_rom_sharing();
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if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) {
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espi_setup();
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espi_configure_decodes();
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}
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}
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