coreboot-kgpe-d16/src/northbridge/amd/amdmct
Marc Jones 067d22340c Fix ECC disable option for AMD Fam10 DDR2 and DDR3.
The logic was backwards on the ECC enable/disable option. Also added better
debug output when the debug RAM init feature is enabled.

Change-Id: I60bffb6149d96cac65011247ef51cd06ed2210c6
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/670
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-02 23:35:26 +01:00
..
mct Fix ECC disable option for AMD Fam10 DDR2 and DDR3. 2012-03-02 23:35:26 +01:00
mct_ddr3 Fix ECC disable option for AMD Fam10 DDR2 and DDR3. 2012-03-02 23:35:26 +01:00
wrappers This patch sets max freq defaults for ddr2 and ddr3for fam10. 2011-06-03 19:59:52 +00:00
amddefs.h remove trailing whitespace 2011-11-01 19:07:45 +01:00