Karthikeyan Ramasubramanian f53214677c util/spd_tools: Encode SDRAM min cycle time (TCKMinPs) ... ADL encodes CK cycle time as tCKMin whereas Sabrina encodes WCK cycle time. Encode tCKMin as per the respective advisories. BUG=None TEST=Generate the SPD and ensure that tCKMin is encoded accordingly. Minimum CAS Latency time is also impacted and is encoded accordingly. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I99ada7ead3a75befb0f934af871eecc060adcb26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>		2022-03-08 23:46:50 +00:00
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set-0	spd/lp5: Add new part H9JCNNNBK3MLYR-N6E	2022-02-15 16:20:50 +00:00
set-1	util/spd_tools: Encode SDRAM min cycle time (TCKMinPs)	2022-03-08 23:46:50 +00:00
memory_parts.json	spd/lp5: Add new part H9JCNNNBK3MLYR-N6E	2022-02-15 16:20:50 +00:00
platforms_manifest.generated.txt	spd/lp5: Generate initial SPDs for Sabrina SoC	2022-02-10 12:50:19 +00:00