4f14cd8a39
If stage cache is enabled, we should not allow S3 resume to load firmware from non-volatile memory. This also adds board reset for failing to load postcar from stage cache. Change-Id: Ib6cc7ad0fe9dcdf05b814d324b680968a2870f23 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
14 lines
349 B
Text
14 lines
349 B
Text
CONFIG_USE_BLOBS=y
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CONFIG_VENDOR_GOOGLE=y
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CONFIG_BOARD_GOOGLE_REEF=y
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CONFIG_CHROMEOS=y
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CONFIG_ADD_FSP_BINARIES=y
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CONFIG_ELOG_GSMI=y
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CONFIG_ELOG_BOOT_COUNT=y
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CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET=144
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CONFIG_SPI_FLASH_SMM=y
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# CONFIG_CONSOLE_SERIAL is not set
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CONFIG_CMOS_POST=y
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CONFIG_CMOS_POST_OFFSET=0x70
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CONFIG_CMOS_POST_EXTRA=y
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CONFIG_PAYLOAD_NONE=y
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