f7daa0bbaf
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2939 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
108 lines
3.5 KiB
C
108 lines
3.5 KiB
C
/*
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* This file is part of the LinuxBIOS project.
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*
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* Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License v2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* Based on other VIA SB code. */
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ops.h>
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#include <device/pci_ids.h>
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#include <console/console.h>
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#include "vt8237r.h"
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#include "chip.h"
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/**
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* No native mode. Interrupts from unconnected HDDs might occur if
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* IRQ14/15 is used for PCI. Therefore no native mode support.
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*/
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static void ide_init(struct device *dev)
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{
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struct southbridge_via_vt8237r_config *sb =
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(struct southbridge_via_vt8237r_config *)dev->chip_info;
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u8 enables;
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u32 cablesel;
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printk_info("%s IDE interface %s\n", "Primary",
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sb->ide0_enable ? "enabled" : "disabled");
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printk_info("%s IDE interface %s\n", "Secondary",
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sb->ide1_enable ? "enabled" : "disabled");
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enables = pci_read_config8(dev, IDE_CS) & ~0x3;
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enables |= (sb->ide0_enable << 1) | sb->ide1_enable;
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pci_write_config8(dev, IDE_CS, enables);
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enables = pci_read_config8(dev, IDE_CS);
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printk_debug("Enables in reg 0x40 read back as 0x%x\n", enables);
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/* Enable only compatibility mode. */
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enables = pci_read_config8(dev, IDE_CONF_II);
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enables &= ~0xc0;
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pci_write_config8(dev, IDE_CONF_II, enables);
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enables = pci_read_config8(dev, IDE_CONF_II);
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printk_debug("Enables in reg 0x42 read back as 0x%x\n", enables);
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/* Enable prefetch buffers. */
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enables = pci_read_config8(dev, IDE_CONF_I);
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enables |= 0xf0;
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pci_write_config8(dev, IDE_CONF_I, enables);
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/* Flush FIFOs at half. */
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enables = pci_read_config8(dev, IDE_CONF_FIFO);
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enables &= 0xf0;
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enables |= (1 << 2) | (1 << 0);
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pci_write_config8(dev, IDE_CONF_FIFO, enables);
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/* PIO read prefetch counter, Bus Master IDE Status Reg. Read Retry. */
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enables = pci_read_config8(dev, IDE_MISC_I);
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enables &= 0xe2;
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enables |= (1 << 4) | (1 << 3);
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pci_write_config8(dev, IDE_MISC_I, enables);
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/* Use memory read multiple, Memory-Write-and-Invalidate. */
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enables = pci_read_config8(dev, IDE_MISC_II);
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enables |= (1 << 2) | (1 << 3);
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pci_write_config8(dev, IDE_MISC_II, enables);
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/* Force interrupts to use compat mode. */
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pci_write_config8(dev, PCI_INTERRUPT_PIN, 0x0);
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pci_write_config8(dev, PCI_INTERRUPT_LINE, 0xff);
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/* Cable guy... */
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cablesel = pci_read_config32(dev, IDE_UDMA);
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cablesel &= ~((1 << 28) | (1 << 20) | (1 << 12) | (1 << 4));
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cablesel |= (sb->ide0_80pin_cable << 28) |
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(sb->ide0_80pin_cable << 20) |
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(sb->ide1_80pin_cable << 12) |
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(sb->ide1_80pin_cable << 4);
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pci_write_config32(dev, IDE_UDMA, cablesel);
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}
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static const struct device_operations ide_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = ide_init,
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.enable = 0,
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.ops_pci = 0,
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};
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static const struct pci_driver northbridge_driver __pci_driver = {
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.ops = &ide_ops,
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.vendor = PCI_VENDOR_ID_VIA,
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.device = PCI_DEVICE_ID_VIA_82C586_1,
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};
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