cca50852fe
TEST=Build and boot soraka/eve Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I10de3ff75a3b063c4c46471e380bbbe2630c35f3 Reviewed-on: https://review.coreboot.org/22361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
350 lines
7.4 KiB
Text
350 lines
7.4 KiB
Text
config SOC_INTEL_SKYLAKE
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bool
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help
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Intel Skylake support
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config SOC_INTEL_KABYLAKE
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bool
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default n
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select SOC_INTEL_SKYLAKE
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help
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Intel Kabylake support
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if SOC_INTEL_SKYLAKE
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config CPU_SPECIFIC_OPTIONS
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def_bool y
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select ACPI_INTEL_HARDWARE_SLEEP_VALUES
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select ARCH_BOOTBLOCK_X86_32
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select ARCH_RAMSTAGE_X86_32
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select ARCH_ROMSTAGE_X86_32
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select ARCH_VERSTAGE_X86_32
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select ACPI_NHLT
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select BOOTBLOCK_CONSOLE
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select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
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select BOOT_DEVICE_SUPPORTS_WRITES
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select CACHE_MRC_SETTINGS
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select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE
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select C_ENVIRONMENT_BOOTBLOCK
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select COLLECT_TIMESTAMPS
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select COMMON_FADT
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select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
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select GENERIC_GPIO_LIB
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select HAVE_HARD_RESET
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select HAVE_INTEL_FIRMWARE
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select HAVE_MONOTONIC_TIMER
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select HAVE_SMI_HANDLER
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select IOAPIC
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select NO_FIXED_XIP_ROM_SIZE
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select MRC_SETTINGS_PROTECT
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select PARALLEL_MP
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select PARALLEL_MP_AP_WORK
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select PCIEXP_ASPM
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select PCIEXP_COMMON_CLOCK
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select PCIEXP_CLK_PM
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select PCIEXP_L1_SUB_STATE
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select PCIEX_LENGTH_64MB
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select REG_SCRIPT
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select RELOCATABLE_MODULES
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select RELOCATABLE_RAMSTAGE
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select RTC
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select SA_ENABLE_DPR
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select SOC_INTEL_COMMON
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select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
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select SOC_INTEL_COMMON_BLOCK
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select SOC_INTEL_COMMON_BLOCK_CPU
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select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
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select SOC_INTEL_COMMON_BLOCK_EBDA
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select SOC_INTEL_COMMON_BLOCK_FAST_SPI
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select SOC_INTEL_COMMON_BLOCK_GPIO
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select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL
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select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS
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select SOC_INTEL_COMMON_BLOCK_GSPI
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select SOC_INTEL_COMMON_BLOCK_ITSS
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select SOC_INTEL_COMMON_BLOCK_I2C
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select SOC_INTEL_COMMON_BLOCK_LPC
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select SOC_INTEL_COMMON_BLOCK_LPSS
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select SOC_INTEL_COMMON_BLOCK_PCIE
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select SOC_INTEL_COMMON_BLOCK_PMC
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select SOC_INTEL_COMMON_BLOCK_PCR
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select SOC_INTEL_COMMON_BLOCK_RTC
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select SOC_INTEL_COMMON_BLOCK_SA
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select SOC_INTEL_COMMON_BLOCK_SATA
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select SOC_INTEL_COMMON_BLOCK_SCS
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select SOC_INTEL_COMMON_BLOCK_SGX
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select SOC_INTEL_COMMON_BLOCK_SMBUS
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select SOC_INTEL_COMMON_BLOCK_SPI
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select SOC_INTEL_COMMON_BLOCK_TIMER
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select SOC_INTEL_COMMON_BLOCK_UART
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select SOC_INTEL_COMMON_BLOCK_XHCI
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select SOC_INTEL_COMMON_NHLT
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select SOC_INTEL_COMMON_RESET
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select SOC_INTEL_COMMON_SPI_FLASH_PROTECT
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select SMM_TSEG
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select SMP
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select SSE2
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select SUPPORT_CPU_UCODE_IN_CBFS
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select TSC_CONSTANT_RATE
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select TSC_MONOTONIC_TIMER
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select TSC_SYNC_MFENCE
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select UDELAY_TSC
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select ACPI_NHLT
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select HAVE_FSP_GOP
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select SOC_INTEL_COMMON_GFX_OPREGION
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config MAINBOARD_USES_FSP2_0
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bool
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default n
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config USE_FSP2_0_DRIVER
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def_bool y
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depends on MAINBOARD_USES_FSP2_0
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select PLATFORM_USES_FSP2_0
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select INTEL_GMA_ADD_VBT_DATA_FILE if RUN_FSP_GOP
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select POSTCAR_CONSOLE
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select POSTCAR_STAGE
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config USE_FSP1_1_DRIVER
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def_bool y
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depends on !MAINBOARD_USES_FSP2_0
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select PLATFORM_USES_FSP1_1
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select DISPLAY_FSP_ENTRY_POINTS
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config CHROMEOS
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select CHROMEOS_RAMOOPS_DYNAMIC
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config VBOOT
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select VBOOT_EC_SLOW_UPDATE if VBOOT_EC_SOFTWARE_SYNC
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select VBOOT_SEPARATE_VERSTAGE
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select VBOOT_OPROM_MATTERS
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select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT
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select VBOOT_STARTS_IN_BOOTBLOCK
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select VBOOT_VBNV_CMOS
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select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
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config BOOTBLOCK_RESETS
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string
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default "soc/intel/common/reset.c"
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config CBFS_SIZE
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hex
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default 0x200000
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config CPU_ADDR_BITS
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int
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default 36
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config DCACHE_RAM_BASE
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hex
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default 0xfef00000
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config DCACHE_RAM_SIZE
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hex
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default 0x40000
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help
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The size of the cache-as-ram region required during bootblock
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and/or romstage.
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config DCACHE_BSP_STACK_SIZE
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hex
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default 0x4000
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help
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The amount of anticipated stack usage in CAR by bootblock and
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other stages.
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config C_ENV_BOOTBLOCK_SIZE
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hex
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default 0xC000
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config EXCLUDE_NATIVE_SD_INTERFACE
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bool
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default n
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help
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If you set this option to n, will not use native SD controller.
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config HEAP_SIZE
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hex
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default 0x80000
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config IED_REGION_SIZE
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hex
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default 0x400000
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config PCR_BASE_ADDRESS
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hex
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default 0xfd000000
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help
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This option allows you to select MMIO Base Address of sideband bus.
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config SERIAL_CPU_INIT
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bool
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default n
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config SERIRQ_CONTINUOUS_MODE
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bool
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default n
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help
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If you set this option to y, the serial IRQ machine will be
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operated in continuous mode.
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config SMM_RESERVED_SIZE
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hex
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default 0x200000
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config SMM_TSEG_SIZE
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hex
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default 0x800000
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config VGA_BIOS_ID
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string
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default "8086,0406"
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config UART_DEBUG
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bool "Enable UART debug port."
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default n
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select CONSOLE_SERIAL
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select DRIVERS_UART
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select DRIVERS_UART_8250MEM_32
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select NO_UART_ON_SUPERIO
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config UART_FOR_CONSOLE
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int "Index for LPSS UART port to use for console"
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default 2 if DRIVERS_UART_8250MEM
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default 0
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help
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Index for LPSS UART port to use for console:
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0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2
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config SKYLAKE_SOC_PCH_H
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bool
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default n
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help
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Choose this option if you have a PCH-H chipset.
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config CHIPSET_BOOTBLOCK_INCLUDE
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string
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default "soc/intel/skylake/bootblock/timestamp.inc"
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config NHLT_DMIC_2CH
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bool
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default n
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help
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Include DSP firmware settings for 2 channel DMIC array.
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config NHLT_DMIC_4CH
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bool
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default n
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help
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Include DSP firmware settings for 4 channel DMIC array.
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config NHLT_NAU88L25
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bool
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default n
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help
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Include DSP firmware settings for nau88l25 headset codec.
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config NHLT_MAX98357
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bool
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default n
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help
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Include DSP firmware settings for max98357 amplifier.
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config NHLT_SSM4567
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bool
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default n
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help
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Include DSP firmware settings for ssm4567 smart amplifier.
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config NHLT_RT5514
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bool
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default n
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help
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Include DSP firmware settings for rt5514 DSP.
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config NHLT_RT5663
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bool
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default n
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help
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Include DSP firmware settings for rt5663 headset codec.
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config NHLT_MAX98927
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bool
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default n
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help
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Include DSP firmware settings for max98927 amplifier.
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config NHLT_DA7219
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bool
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default n
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help
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Include DSP firmware settings for DA7219 headset codec.
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choice
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prompt "Cache-as-ram implementation"
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default CAR_NEM_ENHANCED
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help
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This option allows you to select how cache-as-ram (CAR) is set up.
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config CAR_NEM_ENHANCED
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bool "Enhanced Non-evict mode"
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select SOC_INTEL_COMMON_BLOCK_CAR
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select INTEL_CAR_NEM_ENHANCED
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help
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A current limitation of NEM (Non-Evict mode) is that code and data sizes
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are derived from the requirement to not write out any modified cache line.
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With NEM, if there is no physical memory behind the cached area,
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the modified data will be lost and NEM results will be inconsistent.
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ENHANCED NEM guarantees that modified data is always
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kept in cache while clean data is replaced.
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config USE_SKYLAKE_FSP_CAR
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bool "Use FSP CAR"
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select FSP_CAR
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help
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Use FSP APIs to initialize & tear Down the Cache-As-Ram.
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endchoice
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config SKIP_FSP_CAR
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bool "Skip cache as RAM setup in FSP"
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default y
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help
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Skip Cache as RAM setup in FSP.
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config SPI_FLASH_INCLUDE_ALL_DRIVERS
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bool
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default n
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config MAX_ROOT_PORTS
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int
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default 24 if PLATFORM_USES_FSP2_0
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default 20 if PLATFORM_USES_FSP1_1
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config NO_FADT_8042
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bool
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default n
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help
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Choose this option if you want to disable 8042 Keyboard
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config SOC_INTEL_COMMON_LPSS_CLOCK_MHZ
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int
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default 120
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config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
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int
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default 2
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config CPU_BCLK_MHZ
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int
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default 100
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# Clock divider parameters for 115200 baud rate
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config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
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hex
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default 0x30
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config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
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hex
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default 0xc35
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endif
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