coreboot-kgpe-d16/src/southbridge/intel/esb6300/bridge1c.c
Edward O'Callaghan 264d265d9c southbridge: Trivial - drop trailing blank lines at EOF
Change-Id: I5484ebb665453777cc3b2561be6e50c787f1a257
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6209
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-08 13:53:21 +02:00

46 lines
1.2 KiB
C

#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include "esb6300.h"
static void bridge1c_init(struct device *dev)
{
/* configuration */
pci_write_config8(dev, 0x1b, 0x30);
// pci_write_config8(dev, 0x3e, 0x07);
pci_write_config8(dev, 0x3e, 0x04); /* parity ignore */
pci_write_config8(dev, 0x6c, 0x0c); /* undocumented */
pci_write_config8(dev, 0xe0, 0x20);
/* SRB enable */
pci_write_config16(dev, 0xe4, 0x0232);
/* Burst size */
pci_write_config8(dev, 0xf0, 0x02);
/* prefetch threshold size */
pci_write_config16(dev, 0xf8, 0x2121);
/* primary latency */
pci_write_config8(dev, 0x0d, 0x28);
/* multi transaction timer */
pci_write_config8(dev, 0x42, 0x08);
}
static struct device_operations pci_ops = {
.read_resources = pci_bus_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_bus_enable_resources,
.init = bridge1c_init,
.scan_bus = pci_scan_bridge,
.ops_pci = 0,
};
static const struct pci_driver pci_driver __pci_driver = {
.ops = &pci_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = PCI_DEVICE_ID_INTEL_6300ESB_PCI_X,
};