Kyösti Mälkki cd7a70f487 soc/intel: Use common romstage code ... This provides stack guards with checking and common entry into postcar. The code in cpu/intel/car/romstage.c is candidate for becoming architectural so function prototype is moved to <arch/romstage.h>. Change-Id: I4c5a9789e7cf3f7f49a4a33e21dac894320a9639 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34893 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2019-08-26 21:08:41 +00:00
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arch	soc/intel: Use common romstage code	2019-08-26 21:08:41 +00:00
cf9_reset.h	coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)	2019-03-08 08:33:24 +00:00
smm.h	arch/x86: add SMM caller	2018-07-02 16:34:54 +00:00