Kyösti Mälkki cd7a70f487 soc/intel: Use common romstage code ... This provides stack guards with checking and common entry into postcar. The code in cpu/intel/car/romstage.c is candidate for becoming architectural so function prototype is moved to <arch/romstage.h>. Change-Id: I4c5a9789e7cf3f7f49a4a33e21dac894320a9639 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34893 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2019-08-26 21:08:41 +00:00
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acpi_tables.c
board_info.txt
devicetree.cb
dsdt.asl	mb: Set coreboot as DSDT's manufacturer model ID	2018-11-23 11:00:40 +00:00
irq_tables.c
Kconfig	mb/*/*/Kconfig: Remove useless comment	2018-11-28 13:53:51 +00:00
Kconfig.name
romstage.c	soc/intel: Use common romstage code	2019-08-26 21:08:41 +00:00