ba03d8de63
Bind the camera sensor and CIO2 devices through the ports and endpoints configuration available in _DSD ACPI object. * Port represents an interface in a device. * Endpoint represents a connection to that interface. BUG=b:38326541 BRANCH=none TEST=Build and boot poppy. Dump and verify that the generated DSDT table has the required entries. Change-Id: I6d822165bb9a0cd6f7d4cdcb36333887953110a3 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/20053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
76 lines
1.8 KiB
Text
76 lines
1.8 KiB
Text
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <variant/ec.h>
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#include <variant/gpio.h>
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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0x05, // DSDT revision: ACPI v5.0
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"COREv4", // OEM id
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"COREBOOT", // OEM table id
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0x20110725 // OEM revision
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)
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{
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/* Some generic macros */
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#include <soc/intel/skylake/acpi/platform.asl>
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/* global NVS and variables */
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#include <soc/intel/skylake/acpi/globalnvs.asl>
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/* CPU */
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#include <soc/intel/skylake/acpi/cpu.asl>
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Scope (\_SB)
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{
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Device (PWRB)
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{
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Name (_HID, EisaId ("PNP0C0C"))
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}
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Device (PCI0)
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{
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/* Image processing unit */
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#include <soc/intel/skylake/acpi/ipu.asl>
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#include <soc/intel/skylake/acpi/systemagent.asl>
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#include <soc/intel/skylake/acpi/pch.asl>
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}
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}
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/* MIPI camera */
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#include "acpi/ipu_mainboard.asl"
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#include "acpi/mipi_camera.asl"
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/* Chrome OS specific */
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#include <vendorcode/google/chromeos/acpi/chromeos.asl>
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/* Chipset specific sleep states */
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#include <soc/intel/skylake/acpi/sleepstates.asl>
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/* Chrome OS Embedded Controller */
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Scope (\_SB.PCI0.LPCB)
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{
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/* ACPI code for EC SuperIO functions */
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#include <ec/google/chromeec/acpi/superio.asl>
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/* ACPI code for EC functions */
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#include <ec/google/chromeec/acpi/ec.asl>
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}
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Scope (\_SB)
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{
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/* Dynamic Platform Thermal Framework */
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#include <variant/acpi/dptf.asl>
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}
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}
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