1a692d8176
Signed-off-by: Thomas Jourdan <thomas.jourdan@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4392 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
211 lines
5.9 KiB
Text
211 lines
5.9 KiB
Text
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com>
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##
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## This program is free software; you can redistribute it and/or
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## modify it under the terms of the GNU General Public License as
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## published by the Free Software Foundation; version 2 of
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## the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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## MA 02110-1301 USA
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##
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##
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## This mainboard requires DCACHE_AS_RAM enabled. It won't work without.
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##
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##
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## Only use the option table in a normal image
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##
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default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
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## CONFIG_XIP_ROM_SIZE must be a power of 2.
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default CONFIG_XIP_ROM_SIZE = 64 * 1024
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include /config/nofailovercalculation.lb
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##
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## Set all of the defaults for an x86 architecture
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##
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arch i386 end
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##
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## Build the objects we have code for in this directory.
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##
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driver mainboard.o
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if CONFIG_HAVE_MP_TABLE object mptable.o end
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if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
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if CONFIG_HAVE_ACPI_TABLES
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object fadt.o
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object acpi_tables.o
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makerule dsdt.c
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depends "$(CONFIG_MAINBOARD)/dsdt.dsl"
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action "iasl -p dsdt -tc $(CONFIG_MAINBOARD)/dsdt.dsl"
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action "mv $(CURDIR)/dsdt.hex dsdt.c"
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end
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object ./dsdt.o
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end
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object reset.o
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if CONFIG_USE_INIT
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makerule ./auto.o
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depends "$(CONFIG_MAINBOARD)/auto.c option_table.h"
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action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/auto.c -o $@"
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end
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else
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makerule ./auto.inc
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depends "$(CONFIG_MAINBOARD)/auto.c option_table.h"
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action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/auto.c -o $@"
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action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
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action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
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end
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end
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##
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## Build our 16 bit and 32 bit coreboot entry code
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##
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mainboardinit cpu/x86/16bit/entry16.inc
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mainboardinit cpu/x86/32bit/entry32.inc
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ldscript /cpu/x86/16bit/entry16.lds
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if CONFIG_USE_INIT
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ldscript /cpu/x86/32bit/entry32.lds
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ldscript /cpu/x86/car/cache_as_ram.lds
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end
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##
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## Build our reset vector (This is where coreboot is entered)
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##
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if CONFIG_USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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else
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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end
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##
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## Include an id string (For safe flashing)
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##
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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##
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## Setup Cache-As-Ram
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##
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mainboardinit cpu/intel/model_6fx/cache_as_ram.inc
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###
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### This is the early phase of coreboot startup
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### Things are delicate and we test to see if we should
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### failover to another image.
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###
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if CONFIG_USE_FALLBACK_IMAGE
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ldscript /arch/i386/lib/failover.lds
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end
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###
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### O.k. We aren't just an intermediary anymore!
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###
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if CONFIG_USE_INIT
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initobject auto.o
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else
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mainboardinit ./auto.inc
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end
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##
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## Include the secondary Configuration files
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##
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dir /pc80
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config chip.h
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chip northbridge/intel/i3100
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device pci_domain 0 on
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device pci 00.0 on end # IMCH
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device pci 00.1 on end # IMCH error status
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device pci 01.0 on end # IMCH EDMA engine
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device pci 02.0 on end # PCIe port A/A0
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device pci 03.0 on end # PCIe port A1
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chip southbridge/intel/i3100
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# PIRQ line -> legacy IRQ mappings
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register "pirq_a_d" = "0x8b808a8a"
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register "pirq_e_h" = "0x85808080"
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device pci 1c.0 on end # PCIe port B0
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device pci 1c.1 off end # PCIe port B1
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device pci 1c.2 off end # PCIe port B2
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device pci 1c.3 off end # PCIe port B3
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device pci 1d.0 on end # USB (UHCI) 1
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device pci 1d.1 on end # USB (UHCI) 2
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device pci 1d.7 on end # USB (EHCI)
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device pci 1e.0 on end # PCI bridge
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device pci 1f.0 on # LPC bridge
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chip superio/intel/i3100
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device pnp 4e.4 on # Com1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 4e.5 on # Com2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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end
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chip superio/smsc/smscsuperio
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device pnp 2e.0 off # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 2e.2 off # Serial Port 4
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io 0x60 = 0x2e8
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irq 0x70 = 3
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end
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device pnp 2e.3 on # Parallel Port
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io 0x60 = 0x378
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irq 0x70 = 7
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drq 0x74 = 2
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end
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device pnp 2e.4 off # Serial Port 3
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io 0x60 = 0x3e8
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irq 0x70 = 4
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end
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device pnp 2e.7 on # PS/2 Keyboard / Mouse
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1 # PS/2 keyboard interrupt
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irq 0x72 = 12 # PS/2 mouse interrupt
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end
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device pnp 2e.a off # Runtime registers
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io 0x60 = 0x600
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end
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end
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end
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device pci 1f.2 on end # SATA
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device pci 1f.3 on end # SMBus
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device pci 1f.4 on end # Performance counters
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end
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end
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device apic_cluster 0 on
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chip cpu/intel/bga956
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device apic 0 on end
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end
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end
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end
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