ce1fb9d4e9
The PMC chips understand both LPC and FWH flash commands. When in FWH mode (MSR_DIVIL_BALL_OPT(0x51400015) = 0x00000f7d on 5536 boards) the Block Locking Registers by default lock the flash chip for write and erase - in addition to any chipset write protection. This patch adds unlock operations before Pm49FL004/2 write and erase, and it includes an svn mv pm49fl004.c pm49fl00x.c Thanks go to Nikolay for this patch. Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com> Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Bari Ari <bari@onelabs.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3332 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 |
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.. | ||
abuild | ||
ADLO | ||
analysis | ||
buildrom | ||
dump_mmcr | ||
flashrom | ||
getpir | ||
inteltool | ||
k8resdump | ||
lbtdump | ||
mkelfImage | ||
mptable | ||
newconfig | ||
nrv2b | ||
nvramtool | ||
optionlist | ||
options | ||
resetcf | ||
romcc | ||
superiotool | ||
vgabios |