ce22c02387
Add the basic build infrastructure and architectural support
required to build for targets using the MIPS architecture.
This will require the addition of cache maintenance.
BUG=chrome-os-partner:31438
TEST=tested on Pistachio FPGA with Depthcharge as payload;
successfully executed payload.
BRANCH=none
Change-Id: I75cfd0536860b6d84b53a567940fe6668d9b2cbb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 758c8cb9a6846e6ca32be409ec5f7a888ac9c888
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Change-Id: I0b9af983bf5032335a519ce2510a0b3aca082edf
Original-Reviewed-on: https://chromium-review.googlesource.com/219740
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8741
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
85 lines
2.4 KiB
C
85 lines
2.4 KiB
C
/*
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* This file is part of the libpayload project.
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*
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* Copyright (C) 2014 Imagination Technologies
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __MIPS_ARCH_CPU_H__
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#define __MIPS_ARCH_CPU_H__
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/*
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* Reading at this address allows to identify the platform the code is running
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* on
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*/
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#define IMG_PLATFORM_ID() (*((unsigned *)0xB8149060))
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#define IMG_PLATFORM_ID_SILICON 0xF00D0006
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#define CP0_COUNT 9
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#define CP0_COMPARE 11
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#define CP0_STATUS 12
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#define CP0_CAUSE 13
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#define CP0_WATCHLO 18
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#define CP0_WATCHHI 19
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/* coprocessor 0 enable */
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#define ST0_CU0 (1 << 28)
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#define C0_CAUSE_DC (1 << 27)
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/***************************************************************************
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* The following section was copied from arch/mips/include/asm/mipsregs.h in
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* the 3.14 kernel tree.
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*/
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/*
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* Macros to access the system control coprocessor
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*/
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#define __read_32bit_c0_register(source, sel) \
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({ int __res; \
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if (sel == 0) \
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__asm__ __volatile__( \
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"mfc0\t%0, " #source "\n\t" \
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: "=r" (__res)); \
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else \
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__asm__ __volatile__( \
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".set\tmips32\n\t" \
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"mfc0\t%0, " #source ", " #sel "\n\t" \
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".set\tmips0\n\t" \
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: "=r" (__res)); \
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__res; \
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})
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#define __write_32bit_c0_register(register, sel, value) \
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do { \
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if (sel == 0) \
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__asm__ __volatile__( \
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"mtc0\t%z0, " #register "\n\t" \
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: : "Jr" ((unsigned int)(value))); \
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else \
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__asm__ __volatile__( \
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".set\tmips32\n\t" \
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"mtc0\t%z0, " #register ", " #sel "\n\t" \
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".set\tmips0" \
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: : "Jr" ((unsigned int)(value))); \
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} while (0)
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/* Shortcuts to access various internal registers, keep adding as needed. */
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#define read_c0_count() __read_32bit_c0_register($9, 0)
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#define write_c0_count(val) __write_32bit_c0_register($9, 0, (val))
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#define read_c0_cause() __read_32bit_c0_register($13, 0)
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#define write_c0_cause(val) __write_32bit_c0_register($13, 0, (val))
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/***************************************************************************/
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#endif /* __MIPS_ARCH_CPU_H__ */
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