542 lines
15 KiB
C
542 lines
15 KiB
C
/*
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* This file is part of the libpayload project.
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*
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* Copyright (C) 2012 secunet Security Networks AG
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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//#define DEBUG_STATUS
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#include <stdlib.h>
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#include <stdint.h>
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#include <string.h>
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#include <libpayload.h>
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#include <pci.h>
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#include <storage/ata.h>
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#include <storage/ahci.h>
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#include "ahci_private.h"
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#ifdef DEBUG_STATUS
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static inline u32 _ahci_clear_status(volatile u32 *const reg,
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const char *const r,
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const char *const f)
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{
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const u32 bits = *reg;
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if (bits)
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*reg = bits;
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printf("ahci: %s: %s == 0x%08x\n", f, r, bits);
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return bits;
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}
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#define ahci_clear_status(p, r) _ahci_clear_status(&(p)->r, #r, __func__)
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#else
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static inline u32 _ahci_clear_status(volatile u32 *const reg)
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{
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const u32 bits = *reg;
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if (bits)
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*reg = bits;
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return bits;
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}
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#define ahci_clear_status(p, r) _ahci_clear_status(&(p)->r)
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#endif
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static inline int ahci_port_is_active(const hba_port_t *const port)
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{
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return (port->sata_status & (HBA_PxSSTS_IPM_MASK | HBA_PxSSTS_DET_MASK))
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== (HBA_PxSSTS_IPM_ACTIVE | HBA_PxSSTS_DET_ESTABLISHED);
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}
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static int ahci_cmdengine_start(hba_port_t *const port)
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{
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/* Wait for the controller to clear CR.
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This shouldn't take too long, but we should time out nevertheless. */
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int timeout = 1000; /* Time out after 1000 * 1us == 1ms. */
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while ((port->cmd_stat & HBA_PxCMD_CR) && timeout--)
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udelay(1);
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if (timeout < 0) {
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printf("ahci: Timeout during start of command engine.\n");
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return 1;
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}
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port->cmd_stat |= HBA_PxCMD_FRE;
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port->cmd_stat |= HBA_PxCMD_ST;
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return 0;
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}
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static int ahci_cmdengine_stop(hba_port_t *const port)
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{
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port->cmd_stat &= ~HBA_PxCMD_ST;
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/* Wait for the controller to clear FR and CR.
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This shouldn't take too long, but we should time out nevertheless. */
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int timeout = 1000; /* Time out after 1000 * 1us == 1ms. */
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while ((port->cmd_stat & (HBA_PxCMD_FR | HBA_PxCMD_CR)) && timeout--)
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udelay(1);
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if (timeout < 0) {
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printf("ahci: Timeout during stopping of command engine.\n");
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return 1;
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}
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port->cmd_stat &= ~HBA_PxCMD_FRE;
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return 0;
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}
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/** Do minimal error recovery. */
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static int ahci_error_recovery(ahci_dev_t *const dev, const u32 intr_status)
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{
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/* Command engine has to be restarted.
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We don't call ahci_cmdengine_stop() here as it also checks
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HBA_PxCMD_FR which won't clear on fatal errors. */
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dev->port->cmd_stat &= ~HBA_PxCMD_ST;
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/* Always clear sata_error. */
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ahci_clear_status(dev->port, sata_error);
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/* Perform COMRESET if appropriate. */
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const u32 tfd = dev->port->taskfile_data;
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if ((tfd & (HBA_PxTFD_BSY | HBA_PxTFD_DRQ)) |
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(intr_status & HBA_PxIS_PCS)) {
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const u32 sctl = dev->port->sata_control & ~HBA_PxSCTL_DET_MASK;
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dev->port->sata_control = sctl | HBA_PxSCTL_DET_COMRESET;
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mdelay(1);
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dev->port->sata_control = sctl;
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}
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if (ahci_port_is_active(dev->port))
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/* Start command engine. */
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return ahci_cmdengine_start(dev->port);
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else
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return -1;
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}
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/** Give a buffer with even address. */
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static u8 *ahci_prdbuf_init(ahci_dev_t *const dev,
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u8 *const user_buf, const size_t len,
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const int out)
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{
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if ((u32)user_buf & 1) {
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printf("ahci: Odd buffer pointer (%p).\n", user_buf);
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if (dev->buf) /* orphaned buffer */
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free((void *)dev->buf - *(dev->buf - 1));
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dev->buf = malloc(len + 2);
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if (!dev->buf)
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return NULL;
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dev->user_buf = user_buf;
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dev->write_back = !out;
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dev->buflen = len;
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if ((u32)dev->buf & 1) {
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dev->buf[0] = 1;
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dev->buf += 1;
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} else {
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dev->buf[0] = 1;
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dev->buf[1] = 2;
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dev->buf += 2;
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}
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if (out)
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memcpy(dev->buf, user_buf, len);
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return dev->buf;
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} else {
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return user_buf;
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}
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}
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static void ahci_prdbuf_finalize(ahci_dev_t *const dev)
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{
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if (dev->buf) {
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if (dev->write_back)
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memcpy(dev->user_buf, dev->buf, dev->buflen);
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free((void *)dev->buf - *(dev->buf - 1));
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}
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dev->buf = NULL;
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dev->user_buf = NULL;
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dev->write_back = 0;
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dev->buflen = 0;
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}
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static ssize_t ahci_cmdslot_exec(ahci_dev_t *const dev)
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{
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const int slotnum = 0; /* We always use the first slot. */
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if (!(dev->port->cmd_stat & HBA_PxCMD_CR))
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return -1;
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/* Trigger command execution. */
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dev->port->cmd_issue |= (1 << slotnum);
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/* Wait for the controller to finish command execution. */
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int timeout = 50000; /* Time out after 50000 * 100us == 5s. */
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while ((dev->port->cmd_issue & (1 << slotnum)) &&
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!(dev->port->intr_status & HBA_PxIS_TFES) &&
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timeout--)
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udelay(100);
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if (timeout < 0) {
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printf("ahci: Timeout during command execution.\n");
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return -1;
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}
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ahci_prdbuf_finalize(dev);
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const u32 intr_status = ahci_clear_status(dev->port, intr_status);
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if (intr_status & (HBA_PxIS_FATAL | HBA_PxIS_PCS)) {
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ahci_error_recovery(dev, intr_status);
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return -1;
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} else {
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return dev->cmdlist[slotnum].prd_bytes;
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}
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}
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static size_t ahci_cmdslot_prepare(ahci_dev_t *const dev,
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u8 *const user_buf, size_t buf_len,
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const int out)
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{
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const int slotnum = 0; /* We always use the first slot. */
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size_t read_count = 0;
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memset((void *)&dev->cmdlist[slotnum],
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'\0', sizeof(dev->cmdlist[slotnum]));
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memset((void *)dev->cmdtable,
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'\0', sizeof(*dev->cmdtable));
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dev->cmdlist[slotnum].cmd = CMD_CFL(FIS_H2D_FIS_LEN);
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dev->cmdlist[slotnum].cmdtable_base = virt_to_phys(dev->cmdtable);
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if (buf_len > 0) {
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size_t prdt_len;
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u8 *buf;
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int i;
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prdt_len = ((buf_len - 1) >> BYTES_PER_PRD_SHIFT) + 1;
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const size_t max_prdt_len = ARRAY_SIZE(dev->cmdtable->prdt);
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if (prdt_len > max_prdt_len) {
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prdt_len = max_prdt_len;
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buf_len = prdt_len << BYTES_PER_PRD_SHIFT;
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}
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dev->cmdlist[slotnum].prdt_length = prdt_len;
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read_count = buf_len;
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buf = ahci_prdbuf_init(dev, user_buf, buf_len, out);
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if (!buf)
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return 0;
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for (i = 0; i < prdt_len; ++i) {
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const size_t bytes =
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(buf_len < BYTES_PER_PRD)
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? buf_len : BYTES_PER_PRD;
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dev->cmdtable->prdt[i].data_base = virt_to_phys(buf);
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dev->cmdtable->prdt[i].flags = PRD_TABLE_BYTES(bytes);
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buf_len -= bytes;
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buf += bytes;
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}
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}
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return read_count;
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}
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static ssize_t ahci_ata_read_sectors(ata_dev_t *const ata_dev,
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const lba_t start, size_t count,
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u8 *const buf)
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{
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ahci_dev_t *const dev = (ahci_dev_t *)ata_dev;
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if (count == 0)
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return 0;
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if (ata_dev->read_cmd == ATA_READ_DMA) {
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if (start >= (1 << 28)) {
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printf("ahci: Sector is not 28-bit addressable.\n");
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return -1;
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} else if (count > 256) {
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printf("ahci: Sector count too high (max. 256).\n");
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count = 256;
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}
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#ifdef CONFIG_STORAGE_64BIT_LBA
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} else if (ata_dev->read_cmd == ATA_READ_DMA_EXT) {
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if (start >= (1ULL << 48)) {
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printf("ahci: Sector is not 48-bit addressable.\n");
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return -1;
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} else if (count > (64 * 1024)) {
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printf("ahci: Sector count too high (max. 65536).\n");
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count = 64 * 1024;
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}
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#endif
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} else {
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printf("ahci: Unsupported ATA read command (0x%x).\n",
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ata_dev->read_cmd);
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return -1;
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}
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const size_t bytes = count << ata_dev->sector_size_shift;
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const size_t bytes_feasible = ahci_cmdslot_prepare(dev, buf, bytes, 0);
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const size_t sectors = bytes_feasible >> ata_dev->sector_size_shift;
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dev->cmdtable->fis[ 0] = FIS_HOST_TO_DEVICE;
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dev->cmdtable->fis[ 1] = FIS_H2D_CMD;
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dev->cmdtable->fis[ 2] = ata_dev->read_cmd;
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dev->cmdtable->fis[ 4] = (start >> 0) & 0xff;
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dev->cmdtable->fis[ 5] = (start >> 8) & 0xff;
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dev->cmdtable->fis[ 6] = (start >> 16) & 0xff;
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dev->cmdtable->fis[ 7] = FIS_H2D_DEV_LBA;
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dev->cmdtable->fis[ 8] = (start >> 24) & 0xff;
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#ifdef CONFIG_STORAGE_64BIT_LBA
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if (ata_dev->read_cmd == ATA_READ_DMA_EXT) {
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dev->cmdtable->fis[ 9] = (start >> 32) & 0xff;
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dev->cmdtable->fis[10] = (start >> 40) & 0xff;
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}
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#endif
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dev->cmdtable->fis[12] = (sectors >> 0) & 0xff;
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dev->cmdtable->fis[13] = (sectors >> 8) & 0xff;
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if (ahci_cmdslot_exec(dev) < 0)
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return -1;
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else
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return dev->cmdlist->prd_bytes >> ata_dev->sector_size_shift;
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}
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static ssize_t ahci_packet_read_cmd(atapi_dev_t *const _dev,
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const u8 *const cmd, const size_t cmdlen,
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u8 *const buf, const size_t buflen)
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{
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ahci_dev_t *const dev = (ahci_dev_t *)_dev;
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if ((cmdlen != 12) && (cmdlen != 16)) {
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printf("ahci: Only 12- and 16-byte packet commands allowed.\n");
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return -1;
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}
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const size_t len = ahci_cmdslot_prepare(dev, buf, buflen, 0);
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u16 byte_limit = MIN(len, 63 * 1024); /* like Linux */
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if (byte_limit & 1) ++byte_limit; /* even limit */
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dev->cmdlist[0].cmd |= CMD_ATAPI;
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dev->cmdtable->fis[0] = FIS_HOST_TO_DEVICE;
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dev->cmdtable->fis[1] = FIS_H2D_CMD;
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dev->cmdtable->fis[2] = ATA_PACKET;
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dev->cmdtable->fis[5] = byte_limit & 0xff;
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dev->cmdtable->fis[6] = byte_limit >> 8;
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memcpy((void *)dev->cmdtable->atapi_cmd, cmd, cmdlen);
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return ahci_cmdslot_exec(dev);
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}
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static int ahci_identify_device(ata_dev_t *const ata_dev, u8 *const buf)
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{
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ahci_dev_t *const dev = (ahci_dev_t *)ata_dev;
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ahci_cmdslot_prepare(dev, buf, 512, 0);
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dev->cmdtable->fis[0] = FIS_HOST_TO_DEVICE;
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dev->cmdtable->fis[1] = FIS_H2D_CMD;
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dev->cmdtable->fis[2] = ata_dev->identify_cmd;
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if ((ahci_cmdslot_exec(dev) < 0) || (dev->cmdlist->prd_bytes != 512))
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return -1;
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else
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return 0;
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}
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static int ahci_dev_init(hba_ctrl_t *const ctrl,
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hba_port_t *const port,
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const int portnum)
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{
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int ret = 1;
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const int ncs = HBA_CAPS_DECODE_NCS(ctrl->caps);
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/* Allocate command list, one command table and received FIS. */
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cmd_t *const cmdlist = memalign(1024, ncs * sizeof(cmd_t));
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cmdtable_t *const cmdtable = memalign(128, sizeof(cmdtable_t));
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rcvd_fis_t *const rcvd_fis = memalign(256, sizeof(rcvd_fis_t));
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/* Allocate our device structure. */
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ahci_dev_t *const dev = calloc(1, sizeof(ahci_dev_t));
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if (!cmdlist || !cmdtable || !rcvd_fis || !dev)
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goto _cleanup_ret;
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memset((void *)cmdlist, '\0', ncs * sizeof(cmd_t));
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memset((void *)cmdtable, '\0', sizeof(*cmdtable));
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memset((void *)rcvd_fis, '\0', sizeof(*rcvd_fis));
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/* Set command list base and received FIS base. */
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if (ahci_cmdengine_stop(port))
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return 1;
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port->cmdlist_base = virt_to_phys(cmdlist);
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port->frameinfo_base = virt_to_phys(rcvd_fis);
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if (ahci_cmdengine_start(port))
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return 1;
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/* Put port into active state. */
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port->cmd_stat |= HBA_PxCMD_ICC_ACTIVE;
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dev->ctrl = ctrl;
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dev->port = port;
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dev->cmdlist = cmdlist;
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dev->cmdtable = cmdtable;
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dev->rcvd_fis = rcvd_fis;
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/* Wait for D2H Register FIS with device' signature. */
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int timeout = 200; /* Time out after 200 * 10ms == 2s. */
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while ((port->taskfile_data & HBA_PxTFD_BSY) && timeout--)
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mdelay(10);
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/* Initialize device or fall through to clean up. */
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switch (port->signature) {
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case HBA_PxSIG_ATA:
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printf("ahci: ATA drive on port #%d.\n", portnum);
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#ifdef CONFIG_STORAGE_ATA
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dev->ata_dev.identify = ahci_identify_device;
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dev->ata_dev.read_sectors = ahci_ata_read_sectors;
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return ata_attach_device(&dev->ata_dev, PORT_TYPE_SATA);
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#endif
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break;
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case HBA_PxSIG_ATAPI:
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printf("ahci: ATAPI drive on port #%d.\n", portnum);
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#ifdef CONFIG_STORAGE_ATAPI
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dev->atapi_dev.identify = ahci_identify_device;
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dev->atapi_dev.packet_read_cmd = ahci_packet_read_cmd;
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return atapi_attach_device(&dev->atapi_dev, PORT_TYPE_SATA);
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#endif
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break;
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default:
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printf("ahci: Unsupported device (signature == 0x%08x) "
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"on port #%d.\n", port->signature, portnum);
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break;
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}
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ret = 2;
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_cleanup_ret:
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/* Clean up (not reached for initialized devices). */
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if (dev)
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free(dev);
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if (!ahci_cmdengine_stop(port)) {
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port->cmdlist_base = 0;
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port->frameinfo_base = 0;
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if (rcvd_fis)
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free((void *)rcvd_fis);
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if (cmdtable)
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free((void *)cmdtable);
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if (cmdlist)
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free((void *)cmdlist);
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}
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return ret;
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}
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static void ahci_port_probe(hba_ctrl_t *const ctrl,
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hba_port_t *const port,
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const int portnum)
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{
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/* If staggered spin-up is supported, spin-up device. */
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if (ctrl->caps & HBA_CAPS_SSS) {
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port->cmd_stat |= HBA_PxCMD_SUD;
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}
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/* Wait 1s if we just told the device to spin up or
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if it's the first port. */
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if ((ctrl->caps & HBA_CAPS_SSS) ||
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!(ctrl->ports_impl & ((1 << (portnum - 1)) - 1))) {
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/* Wait for port to become active. */
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int timeout = 100; /* Time out after 100 * 100us == 10ms. */
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while (!ahci_port_is_active(port) && timeout--)
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udelay(100);
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}
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if (!ahci_port_is_active(port))
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return;
|
|
|
|
ahci_clear_status(port, sata_error);
|
|
ahci_clear_status(port, intr_status);
|
|
|
|
ahci_dev_init(ctrl, port, portnum);
|
|
}
|
|
|
|
#ifdef CONFIG_STORAGE_AHCI_ONLY_TESTED
|
|
static u32 working_controllers[] = {
|
|
0x8086 | 0x2929 << 16,
|
|
};
|
|
#endif
|
|
static void ahci_init_pci(pcidev_t dev)
|
|
{
|
|
int i;
|
|
|
|
const u16 class = pci_read_config16(dev, 0xa);
|
|
if (class != 0x0106)
|
|
return;
|
|
const u16 vendor = pci_read_config16(dev, 0x00);
|
|
const u16 device = pci_read_config16(dev, 0x02);
|
|
|
|
#ifdef CONFIG_STORAGE_AHCI_ONLY_TESTED
|
|
const u32 vendor_device = pci_read_config32(dev, 0x0);
|
|
for (i = 0; i < ARRAY_SIZE(working_controllers); ++i)
|
|
if (vendor_device == working_controllers[i])
|
|
break;
|
|
if (i == ARRAY_SIZE(working_controllers)) {
|
|
printf("ahci: Not using untested SATA controller "
|
|
"%02x:%02x.%02x (%04x:%04x).\n", PCI_BUS(dev),
|
|
PCI_SLOT(dev), PCI_FUNC(dev), vendor, device);
|
|
return;
|
|
}
|
|
#endif
|
|
|
|
printf("ahci: Found SATA controller %02x:%02x.%02x (%04x:%04x).\n",
|
|
PCI_BUS(dev), PCI_SLOT(dev), PCI_FUNC(dev), vendor, device);
|
|
|
|
hba_ctrl_t *const ctrl = phys_to_virt(
|
|
pci_read_config32(dev, 0x24) & ~0x3ff);
|
|
hba_port_t *const ports = ctrl->ports;
|
|
|
|
/* Reset host controller. */
|
|
ctrl->global_ctrl |= HBA_CTRL_RESET;
|
|
/* Reset has to be finished after 1s. */
|
|
delay(1);
|
|
if (ctrl->global_ctrl & HBA_CTRL_RESET) {
|
|
printf("ahci: ERROR: "
|
|
"Controller reset didn't finish within 1s.\n");
|
|
return;
|
|
}
|
|
|
|
/* Set AHCI access mode. */
|
|
ctrl->global_ctrl |= HBA_CTRL_AHCI_EN;
|
|
|
|
/* Probe for devices. */
|
|
for (i = 0; i < 32; ++i) {
|
|
if (ctrl->ports_impl & (1 << i))
|
|
ahci_port_probe(ctrl, &ports[i], i + 1);
|
|
}
|
|
}
|
|
|
|
void ahci_initialize(void)
|
|
{
|
|
int bus, dev, func;
|
|
|
|
for (bus = 0; bus < 256; ++bus) {
|
|
for (dev = 0; dev < 32; ++dev) {
|
|
const u16 class =
|
|
pci_read_config16(PCI_DEV(bus, dev, 0), 0xa);
|
|
if (class != 0xffff) {
|
|
for (func = 0; func < 8; ++func)
|
|
ahci_init_pci(PCI_DEV(bus, dev, func));
|
|
}
|
|
}
|
|
}
|
|
}
|