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coreboot-kgpe-d16/src/cpu/intel/socket_FC_PGA370
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Uwe Hermann af8b2b91b4 Drop unused DCACHE_RAM_BASE from intel/car/cache_as_ram.inc-using sockets. 
This CAR implementation hardcodes the Cache-as-RAM base address to:

  0xd0000 - CacheSize

so the DCACHE_RAM_BASE is never actually used for this implementation
and these sockets.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5953 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-15 07:47:51 +00:00
..
chip.h Create new socket for FCPGA370 and PGA370 CPU's for CAR. Add CAR support for Coppermine FC-PGA CPU's (model_68x). 2010-06-21 19:40:09 +00:00
Kconfig Drop unused DCACHE_RAM_BASE from intel/car/cache_as_ram.inc-using sockets. 2010-10-15 07:47:51 +00:00
Makefile.inc Rename build system variables to be more intuitive, and 2010-09-30 16:55:02 +00:00
socket_FC_PGA370.c Create new socket for FCPGA370 and PGA370 CPU's for CAR. Add CAR support for Coppermine FC-PGA CPU's (model_68x). 2010-06-21 19:40:09 +00:00