coreboot-kgpe-d16/payloads/libpayload
Julius Werner efcee767de CBFS: Automate ROM image layout and remove hardcoded offsets
Non-x86 boards currently need to hardcode the position of their CBFS
master header in a Kconfig. This is very brittle because it is usually
put in between the bootblock and the first CBFS entry, without any
checks to guarantee that it won't overlap either of those. It is not fun
to debug random failures that move and disappear with tiny alignment
changes because someone decided to write "ORBC1112" over some part of
your data section (in a way that is not visible in the symbolized .elf
binaries, only in the final image). This patch seeks to prevent those
issues and reduce the need for manual configuration by making the image
layout a completely automated part of cbfstool.

Since automated placement of the CBFS header means we can no longer
hardcode its position into coreboot, this patch takes the existing x86
solution of placing a pointer to the header at the very end of the
CBFS-managed section of the ROM and generalizes it to all architectures.
This is now even possible with the read-only/read-write split in
ChromeOS, since coreboot knows how large that section is from the
CBFS_SIZE Kconfig (which is by default equal to ROM_SIZE, but can be
changed on systems that place other data next to coreboot/CBFS in ROM).

Also adds a feature to cbfstool that makes the -B (bootblock file name)
argument on image creation optional, since we have recently found valid
use cases for CBFS images that are not the first boot medium of the
device (instead opened by an earlier bootloader that can already
interpret CBFS) and therefore don't really need a bootblock.

BRANCH=None
BUG=None
TEST=Built and booted on Veyron_Pinky, Nyan_Blaze and Falco.

Change-Id: Ib715bb8db258e602991b34f994750a2d3e2d5adf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e9879c0fbd57f105254c54bacb3e592acdcad35c
Original-Change-Id: Ifcc755326832755cfbccd6f0a12104cba28a20af
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/229975
Reviewed-on: http://review.coreboot.org/9620
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-14 09:01:27 +02:00
..
arch arm: Dump additional fault registers in abort handlers 2015-04-08 09:28:37 +02:00
bin libpayload: arch/mips: Add basic MIPS architecture support 2015-03-21 11:07:50 +01:00
configs serial: Combine Tegra and Rockchip UARTs to generic 8250_mmio32 2015-04-10 07:50:21 +02:00
crypto libpayload: Change CONFIG_* to CONFIG_LP_* in the kconfig. 2014-08-05 18:44:08 +02:00
curses libpayload/PDcurses: avoid NULL deref 2015-01-03 23:58:22 +01:00
drivers serial: Combine Tegra and Rockchip UARTs to generic 8250_mmio32 2015-04-10 07:50:21 +02:00
gdb libpayload: Let GDB stub read/write memory with aligned MMIO words 2015-01-12 05:56:16 +01:00
include CBFS: Automate ROM image layout and remove hardcoded offsets 2015-04-14 09:01:27 +02:00
libc libpayload: Add RAM code to sysinfo_t 2015-03-21 11:04:03 +01:00
libcbfs CBFS: Automate ROM image layout and remove hardcoded offsets 2015-04-14 09:01:27 +02:00
liblzma LZMA: Add a version of ulzma which takes the input and output buffer sizes. 2014-08-10 22:29:51 +02:00
libpci libpayload: minor cleanups 2012-04-04 00:40:31 +02:00
sample libpayload: Fix missed CONFIG_ -> CONFIG_LP_ substitutions 2014-10-17 11:24:15 +02:00
tests libpayload: Change CONFIG_X86_SERIAL_CONSOLE to CONFIG_8250_SERIAL_CONSOLE 2014-08-28 01:40:48 +02:00
util libpayload: arch/mips: Add basic MIPS architecture support 2015-03-21 11:07:50 +01:00
Config.in serial: Combine Tegra and Rockchip UARTs to generic 8250_mmio32 2015-04-10 07:50:21 +02:00
Doxyfile Run doxygen -u on doxygen configuration files 2010-06-28 10:40:38 +00:00
LICENSES libpayload: Introduce new Kconfig to explicitly allow GPL code 2015-01-09 07:06:27 +01:00
LICENSE_GPL libpayload: Introduce new Kconfig to explicitly allow GPL code 2015-01-09 07:06:27 +01:00
Makefile libpayload: arch/mips: Add basic MIPS architecture support 2015-03-21 11:07:50 +01:00
Makefile.inc libpayload: arch/mips: Add basic MIPS architecture support 2015-03-21 11:07:50 +01:00
README libpayload, superiotool: README: Prepend `coreboot/` to path of change directory line 2013-04-04 17:22:15 +02:00

README

-------------------------------------------------------------------------------
libpayload README
-------------------------------------------------------------------------------

libpayload is a minimal library to support standalone payloads
that can be booted with firmware like coreboot. It handles the setup
code, and provides common C library symbols such as malloc() and printf().

Note: This is _not_ a standard library for use with an operating system,
rather it's only useful for coreboot payload development!
See http://coreboot.org for details on coreboot.


Installation
------------

 $ git clone http://review.coreboot.org/p/coreboot.git

 $ cd coreboot/payloads/libpayload

 $ make menuconfig

 $ make

 $ sudo make install (optional, will install into /opt per default)

As libpayload is for 32bit x86 systems only, you might have to install the
32bit libgcc version, otherwise your payloads will fail to compile.
On Debian systems you'd do 'apt-get install gcc-multilib' for example.


Usage
-----

Here's an example of a very simple payload (hello.c) and how to build it:

 #include <libpayload.h>

 int main(void)
 {
     printf("Hello, world!\n");
     return 0;
 }

Building the payload using the 'lpgcc' compiler wrapper:

 $ lpgcc -o hello.elf hello.c

Please see the sample/ directory for details.


Website and Mailing List
------------------------

The main website is http://www.coreboot.org/Libpayload.

For additional information, patches, and discussions, please join the
coreboot mailing list at http://coreboot.org/Mailinglist, where most
libpayload developers are subscribed.


Copyright and License
---------------------

See LICENSES.