coreboot-kgpe-d16/src/mainboard/lenovo/x201/dsdt.asl
Vladimir Serbinenko d2aa4730e3 mb/{lenovo/x201,packardbell/ms2290}/acpi: Merge common platform ASL code
This code in reality just describes the southbridge features, don't put a copy
in every mainboard.

This commit follows up on commit e288758b with Change-Id
I8cf3019a36b1ae6a17d502e7508f36ea9fa62830 ("bd82x6x: Merge common
platform ASL code").

Change-Id: Ic5260461165b794a13efd2c6d968c953f60dd253
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36229
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-23 13:36:15 +00:00

95 lines
2.3 KiB
Text

/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#define THINKPAD_EC_GPE 17
#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
#define EC_LENOVO_H8_ME_WORKAROUND 1
#include <arch/acpi.h>
DefinitionBlock(
"dsdt.aml",
"DSDT",
0x02, /* DSDT revision: ACPI v2.0 and up */
OEM_ID,
ACPI_TABLE_CREATOR,
0x20130325 /* OEM revision */
)
{
#include <southbridge/intel/bd82x6x/acpi/platform.asl>
/* Some generic macros */
#include "acpi/platform.asl"
/* global NVS and variables */
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
/* General Purpose Events */
#include "acpi/gpe.asl"
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)
{
#include <northbridge/intel/nehalem/acpi/nehalem.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
}
Device (UNCR)
{
Name (_BBN, 0xFF)
Name (_ADR, 0x00)
Name (RID, 0x00)
Name (_HID, EisaId ("PNP0A03"))
Name (_CRS, ResourceTemplate ()
{
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, /* Granularity */
0x00FF, /* Range Minimum */
0x00FF, /* Range Maximum */
0x0000, /* Translation Offset */
0x0001, /* Length */
,, )
})
Device (SAD)
{
Name (_ADR, 0x01)
Name (RID, 0x00)
OperationRegion (SADC, PCI_Config, 0x00, 0x0100)
Field (SADC, DWordAcc, NoLock, Preserve)
{
Offset (0x40),
PAM0, 8,
PAM1, 8,
PAM2, 8,
PAM3, 8,
PAM4, 8,
PAM5, 8,
PAM6, 8
}
}
}
}
/* Chipset specific sleep states */
#include <southbridge/intel/i82801gx/acpi/sleepstates.asl>
/* Dock support code */
#include "acpi/dock.asl"
}