ce128a7ef1
Add ALC286 commands and update the PLATFORM_CONFIGURATION structure with the list address. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit 2dd5cd2f01cd37c9eb7dff85e20e446c7d5ab2ee) Change-Id: I037b39a8634bf886f82ed93488f1efbf6661c93f Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17226 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
150 lines
4.6 KiB
C
150 lines
4.6 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015-2016 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <northbridge/amd/pi/agesawrapper.h>
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#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
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static const PCIe_PORT_DESCRIPTOR PortList [] = {
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/* Initialize Port descriptor (PCIe port, Lanes 7:4, D2F1) for x4 slot */
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 4, 7),
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PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1,
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HotplugDisabled,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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AspmL0sL1, 0x04, 0)
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},
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/* Initialize Port descriptor (PCIe port, Lanes 1:0, D2F2) for M.2 */
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 0, 1),
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PCIE_PORT_DATA_INITIALIZER_V2 (PortDisabled, ChannelTypeExt6db, 2, 2,
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HotplugDisabled,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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AspmL0sL1, 0x17, 0)
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},
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 1, 1),
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PCIE_PORT_DATA_INITIALIZER_V2 (PortDisabled, ChannelTypeExt6db, 2, 3,
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HotplugDisabled,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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AspmL0sL1, 0x17, 0)
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},
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/* Initialize Port descriptor (PCIe port, Lane 2, D2F4) for x1 slot */
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2),
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PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4,
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HotplugDisabled,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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AspmL0sL1, 0x13, 0)
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},
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/* Initialize Port descriptor (PCIe port, Lane3, D2F5) for SD */
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{
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DESCRIPTOR_TERMINATE_LIST,
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PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3),
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PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5,
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HotplugDisabled,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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AspmL0sL1, 0x16, 0)
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},
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/* Initialize Port descriptor (PCIe port, Lane 1, D2F3) for M.2 */
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};
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static const PCIe_DDI_DESCRIPTOR DdiList [] = {
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/* DDI0 - eDP */
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11),
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PCIE_DDI_DATA_INITIALIZER (ConnectorTypeEDP, Aux1, Hdp1)
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},
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/* DDI1 - DP */
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),
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PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2)
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},
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/* DDI2 - HDMI */
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{
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DESCRIPTOR_TERMINATE_LIST,
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PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 19),
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PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux3, Hdp3)
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},
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};
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static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
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.Flags = DESCRIPTOR_TERMINATE_LIST,
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.SocketId = 0,
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.PciePortList = PortList,
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.DdiLinkList = DdiList
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};
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static const UINT32 AzaliaCodecAlc286Table[] =
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{
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0x00172051, 0x001721C7, 0x00172222, 0x00172310,
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0x0017FF00, 0x0017FF00, 0x0017FF00, 0x0017FF00,
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0x01271C50, 0x01271D01, 0x01271EA6, 0x01271FB7,
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0x01371C00, 0x01371D00, 0x01371E00, 0x01371F40,
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0x01471C10, 0x01471D01, 0x01471E17, 0x01471F90,
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0x01771CF0, 0x01771D11, 0x01771E11, 0x01771F41,
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0x01871C40, 0x01871D10, 0x01871EA1, 0x01871F04,
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0x01971CF0, 0x01971D11, 0x01971E11, 0x01971F41,
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0x01A71CF0, 0x01A71D11, 0x01A71E11, 0x01A71F41,
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0x01D71C2D, 0x01D71DA5, 0x01D71E67, 0x01D71F40,
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0x01E71C30, 0x01E71D11, 0x01E71E45, 0x01E71F04,
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0x02171C20, 0x02171D10, 0x02171E21, 0x02171F04,
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0x02050071, 0x02040014, 0x02050010, 0x02040C22,
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0x0205004F, 0x0204B029, 0x0205002B, 0x02040C50,
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0x0205002D, 0x02041020, 0x02050020, 0x02040000,
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0x02050019, 0x02040817, 0x02050035, 0x02041AA5,
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0x02050063, 0x02042906, 0x02050063, 0x02042906,
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0xffffffff
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};
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CONST CODEC_VERB_TABLE_LIST CodecTableList[] =
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{
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{ (UINT32) 0x10ec0286, AzaliaCodecAlc286Table},
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{ (UINT32) 0x0FFFFFFFF, (UINT32 *)0x0FFFFFFFF}
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};
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/*---------------------------------------------------------------------------------------*/
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/**
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* OemCustomizeInitEarly
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*
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* Description:
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* This is the stub function will call the host environment through the binary block
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* interface (call-out port) to provide a user hook opportunity
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*
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* Parameters:
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* @param[in] **PeiServices
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* @param[in] *InitEarly
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*
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* @retval VOID
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*
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**/
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/*---------------------------------------------------------------------------------------*/
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VOID OemCustomizeInitEarly (
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IN OUT AMD_EARLY_PARAMS *InitEarly
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)
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{
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InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
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InitEarly->PlatformConfig.AzaliaCodecVerbTable = (UINT64)(UINTN)CodecTableList;
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}
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