91135fef22
Use bettong as the reference for the gardenia mainboard. Update makefiles etc so it builds. This patch intentionlly keeps the carrizo_fch.asl file to remain synchronized with the AMD PI package. Remove items that do not apply to the Stoney APU, rewrite the comments associated with the PCIe devices, and fix up the SPD register association to match the 00670F00 chip.h. Original-Signed-off-by: Marc Jones <marcj303@gmail.com> Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> (cherry picked from commit 82accfcf9ec76a042156fb6e528f7900987b6e7e) Change-Id: I014fec5c99c01fc02e129be514b704c8ba27d464 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17218 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
109 lines
3.8 KiB
Text
109 lines
3.8 KiB
Text
#*****************************************************************************
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#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2015 Advanced Micro Devices, Inc.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#*****************************************************************************
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entries
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#start-bit length config config-ID name
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#0 8 r 0 seconds
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#8 8 r 0 alarm_seconds
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#16 8 r 0 minutes
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#24 8 r 0 alarm_minutes
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#32 8 r 0 hours
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#40 8 r 0 alarm_hours
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#48 8 r 0 day_of_week
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#56 8 r 0 day_of_month
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#64 8 r 0 month
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#72 8 r 0 year
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#80 4 r 0 rate_select
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#84 3 r 0 REF_Clock
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#87 1 r 0 UIP
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#88 1 r 0 auto_switch_DST
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#89 1 r 0 24_hour_mode
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#90 1 r 0 binary_values_enable
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#91 1 r 0 square-wave_out_enable
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#92 1 r 0 update_finished_enable
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#93 1 r 0 alarm_interrupt_enable
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#94 1 r 0 periodic_interrupt_enable
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#95 1 r 0 disable_clock_updates
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#96 288 r 0 temporary_filler
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0 384 r 0 reserved_memory
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384 1 e 4 boot_option
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386 1 e 1 ECC_memory
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388 4 h 0 reboot_counter
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392 3 e 5 baud_rate
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395 1 e 1 hw_scrubber
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396 1 e 1 interleave_chip_selects
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397 2 e 8 max_mem_clock
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399 1 e 2 multi_core
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400 1 e 1 power_on_after_fail
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412 4 e 6 debug_level
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416 4 e 7 boot_first
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420 4 e 7 boot_second
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424 4 e 7 boot_third
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428 4 h 0 boot_index
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432 8 h 0 boot_countdown
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440 4 e 9 slow_cpu
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444 1 e 1 nmi
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445 1 e 1 iommu
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728 256 h 0 user_data
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984 16 h 0 check_sum
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# Reserve the extended AMD configuration registers
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1000 24 r 0 amd_reserved
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enumerations
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#ID value text
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1 0 Disable
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1 1 Enable
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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5 0 115200
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5 1 57600
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5 2 38400
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5 3 19200
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5 4 9600
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5 5 4800
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5 6 2400
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5 7 1200
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6 6 Notice
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6 7 Info
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6 8 Debug
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6 9 Spew
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7 0 Network
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7 1 HDD
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7 2 Floppy
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7 8 Fallback_Network
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7 9 Fallback_HDD
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7 10 Fallback_Floppy
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#7 3 ROM
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8 0 400Mhz
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8 1 333Mhz
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8 2 266Mhz
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8 3 200Mhz
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9 0 off
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9 1 87.5%
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9 2 75.0%
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9 3 62.5%
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9 4 50.0%
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9 5 37.5%
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9 6 25.0%
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9 7 12.5%
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checksums
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checksum 392 983 984
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