387 lines
16 KiB
HTML
387 lines
16 KiB
HTML
<!DOCTYPE html>
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<html>
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<head>
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<title>SoC</title>
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</head>
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<body>
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<h1>x86 System on a Chip (SoC) Development</h1>
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<p>
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SoC development is best done in parallel with development for a specific
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board. The combined steps are listed
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<a target="_blank" href="../development.html">here</a>.
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The development steps for the SoC are listed below:
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</p>
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<ol>
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<li><a target="_blank" href="../fsp1_1.html#RequiredFiles">FSP 1.1</a> required files</li>
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<li>SoC <a href="#RequiredFiles">Required Files</a></li>
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<li><a href="#Descriptor">Start Booting</a></li>
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<li><a href="#EarlyDebug">Early Debug</a></li>
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<li><a href="#Bootblock">Bootblock</a></li>
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<li><a href="#TempRamInit">TempRamInit</a></li>
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<li><a href="#Romstage">Romstage</a>
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<ol type="A">
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<li>Enable <a href="#SerialOutput">Serial Output"</a></li>
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<li>Get the <a href="#PreviousSleepState">Previous Sleep State</a></li>
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<li>Add the <a href="#MemoryInit">MemoryInit</a> Support</li>
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</ol>
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</li>
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</ol>
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<hr>
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<h1><a name="RequiredFiles">Required Files</a></h1>
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<p>
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Create the directory as src/soc/<Vendor>/<Chip Family>.
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</p>
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<p>
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The following files are required to build a new SoC:
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</p>
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<ul>
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<li>Include files
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<ul>
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<li>include/soc/pei_data.h</li>
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<li>include/soc/pm.h</li>
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</ul>
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</li>
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<li>Kconfig - Defines the Kconfig value for the SoC and selects the tool
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chains for the various stages:
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<ul>
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<li>select ARCH_BOOTBLOCK_<Tool Chain></li>
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<li>select ARCH_RAMSTAGE_<Tool Chain></li>
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<li>select ARCH_ROMSTAGE_<Tool Chain></li>
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<li>select ARCH_VERSTAGE_<Tool Chain></li>
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</ul>
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</li>
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<li>Makefile.inc - Specify the include paths</li>
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<li>memmap.c - Top of usable RAM</li>
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</ul>
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<hr>
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<h1><a name="Descriptor">Start Booting</a></h1>
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<p>
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Some SoC parts require additional firmware components in the flash.
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This section describes how to add those pieces.
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</p>
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<h2>Intel Firmware Descriptor</h2>
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<p>
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The Intel Firmware Descriptor (IFD) is located at the base of the flash part.
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The following command overwrites the base of the flash image with the Intel
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Firmware Descriptor:
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</p>
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<pre><code>dd if=descriptor.bin of=build/coreboot.rom conv=notrunc >/dev/null 2>&1</code></pre>
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<h2><a name="MEB">Management Engine Binary</a></h2>
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<p>
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Some SoC parts contain and require that the Management Engine (ME) be running
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before it is possible to bring the x86 processor out of reset. A binary file
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containing the management engine code must be added to the firmware using the
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ifdtool. The following commands add this binary blob:
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</p>
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<pre><code>util/ifdtool/ifdtool -i ME:me.bin build/coreboot.rom
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mv build/coreboot.rom.new build/coreboot.rom
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</code></pre>
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<h2><a name="EarlyDebug">Early Debug</a></h2>
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<p>
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Early debugging between the reset vector and the time the serial port is enabled
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is most easily done by writing values to port 0x80.
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</p>
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<h2>Success</h2>
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<p>
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When the reset vector is successfully invoked, port 0x80 will output the following value:
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</p>
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<ul>
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<li>0x01: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l45">POST_RESET_VECTOR_CORRECT</a>
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- Bootblock successfully executed the
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<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/reset16.inc;hb=HEAD#l4">reset vector</a>
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and entered the 16-bit code at
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<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/entry16.inc;hb=HEAD#l35">_start</a>
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</li>
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</ul>
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<hr>
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<h1><a name="Bootblock">Bootblock</a></h1>
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<p>
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Implement the bootblock using the following steps:
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</p>
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<ol>
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<li>Create the directory as src/soc/<Vendor>/<Chip Family>/bootblock</li>
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<li>Add the timestamp.inc file which initializes the floating point registers and saves
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the initial timestamp.
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</li>
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<li>Add the bootblock.c file which:
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<ol type="A">
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<li>Enables memory-mapped PCI config access</li>
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<li>Updates the microcode by calling intel_update_microcode_from_cbfs</li>
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<li>Enable ROM caching</li>
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</ol>
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</li>
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<li>Edit the src/soc/<Vendor>/<Chip Family>/Kconfig file
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<ol type="A">
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<li>Add the BOOTBLOCK_CPU_INIT value to point to the bootblock.c file</li>
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<li>Add the CHIPSET_BOOTBLOCK_INCLUDE value to point to the timestamp.inc file</li>
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</ol>
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</li>
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<li>Edit the src/soc/<Vendor>/<Chip Family>/Makefile.inc file
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<ol type="A">
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<li>Add the bootblock subdirectory</li>
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</ol>
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</li>
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<li>Edit the src/soc/<Vendor>/<Chip Family>/memmap.c file
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<ol type="A">
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<li>Add the fsp/memmap.h include file</li>
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<li>Add the mmap_region_granularity routine</li>
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</ol>
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</li>
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<li>Add the necessary .h files to define the necessary values and structures</li>
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<li>When successful port 0x80 will output the following values:
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<ol type="A">
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<li>0x01: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l45">POST_RESET_VECTOR_CORRECT</a>
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- Bootblock successfully executed the
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<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/reset16.inc;hb=HEAD#l4">reset vector</a>
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and entered the 16-bit code at
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<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/entry16.inc;hb=HEAD#l35">_start</a>
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</li>
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<li>0x10: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l53">POST_ENTER_PROTECTED_MODE</a>
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- Bootblock executing in
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<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/32bit/entry32.inc;hb=HEAD#l55">32-bit mode</a>
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</li>
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<li>0x10 - Verstage/romstage reached 32-bit mode</li>
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</ol>
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</li>
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</ol>
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<p>
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<b>Build Note:</b> The following files are included into the default bootblock image:
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</p>
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<ul>
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<li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/bootblock_romcc.S;hb=HEAD">src/arch/x86/bootblock_romcc.S</a>
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added by <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makefile.inc;hb=HEAD#l133">src/arch/x86/Makefile.inc</a>
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and includes the following files:
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<ul>
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<li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/prologue.inc">src/arch/x86/prologue.inc</a></li>
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<li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/reset16.inc">src/cpu/x86/16bit/reset16.inc</a></li>
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<li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/entry16.inc">src/cpu/x86/16bit/entry16.inc</a></li>
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<li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/32bit/entry32.inc">src/cpu/x86/32bit/entry32.inc</a></li>
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<li>The code in
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<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/bootblock_romcc.S">src/arch/x86/bootblock_romcc.S</a>
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includes src/soc/<Vendor>/<Chip Family>/bootblock/timestamp.inc using the
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CONFIG_CHIPSET_BOOTBLOCK_INCLUDE value set above
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</li>
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<li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/sse_enable.inc">src/cpu/x86/sse_enable.inc</a></li>
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<li>The code in
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<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makefile.inc;hb=HEAD#l156">src/arch/x86/Makefile.inc</a>
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invokes the ROMCC tool to convert the following "C" code into assembler as bootblock.inc:
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<ul>
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<li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/include/arch/bootblock_romcc.h">src/arch/x86/include/arch/bootblock_romcc.h</a></li>
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<li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/lapic/boot_cpu.c">src/cpu/x86/lapic/boot_cpu.c</a></li>
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<li>The CONFIG_BOOTBLOCK_CPU_INIT value set above typically points to the code in
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src/soc/<Vendor>/<Chip Family>/bootblock/bootblock.c
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</li>
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</ul>
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</li>
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</ul>
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</li>
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<li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/id.S">src/arch/x86/id.S</a>
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added by <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makefile.inc;hb=HEAD#l110">src/arch/x86/Makefile.inc</a>
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</li>
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<li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/intel/fit/fit.S">src/cpu/intel/fit/fit.S</a>
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added by <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/intel/fit/Makefile.inc;hb=HEAD">src/cpu/intel/fit/Makefile.inc</a>
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</li>
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<li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/walkcbfs.S">src/arch/x86/walkcbfs.S</a>
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added by <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makefile.inc;hb=HEAD#l137">src/arch/x86/Makefile.inc</a>
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</li>
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</ul>
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<hr>
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<h1><a name="TempRamInit">TempRamInit</a></h1>
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<p>
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Enable the call to TempRamInit in two stages:
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</p>
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<ol>
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<li>Finding the FSP binary in the read-only CBFS region</li>
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<li>Call TempRamInit</li>
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</ol>
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<h2>Find FSP Binary</h2>
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<p>
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Use the following steps to locate the FSP binary:
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</p>
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<ol>
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<li>Edit the src/soc/<Vendor>/<Chip Family>/Kconfig file
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<ol type="A">
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<li>Add "select USE_GENERIC_FSP_CAR_INC" to enable the use of
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<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc">src/drivers/intel/fsp1_1/cache_as_ram.inc</a>
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</li>
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<li>Add "select SOC_INTEL_COMMON" to enable the use of the files from src/soc/intel/common
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specifically building
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<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/soc/intel/common/util.c">util.c</a>
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</li>
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</ol>
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</li>
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<li>Debug the result until port 0x80 outputs
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<ol type="A">
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<li>0x90: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205">POST_FSP_TEMP_RAM_INIT</a>
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- Just before calling
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<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l73">TempRamInit</a>
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</li>
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<li>Alternating 0xba and 0x01 - The FSP image was not found</li>
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</ol>
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</li>
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<li>Add the <a target="_blank" href="../fsp1_1.html#FspBinary">FSP binary file</a> to the flash image</li>
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<li>Set the following Kconfig values:
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<ul>
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<li>CONFIG_FSP_LOC to the FSP base address specified in the previous step</li>
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<li>CONFIG_FSP_IMAGE_ID_STRING</li>
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</ul>
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</li>
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<li>Debug the result until port 0x80 outputs
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<ol type="A">
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<li>0x90: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205">POST_FSP_TEMP_RAM_INIT</a>
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- Just before calling
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<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l73">TempRamInit</a>
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</li>
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<li>Alternating 0xbb and 0x02 - TempRamInit executed, no CPU microcode update found</li>
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</ol>
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</li>
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</ol>
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<h2>Calling TempRamInit</h2>
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<p>
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Use the following steps to debug the call to TempRamInit:
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</p>
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<ol>
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<li>Add the CPU microcode update file
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<ol type="A">
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<li>Add the microcode file with the following command
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<pre><code>util/cbfstool/cbfstool build/coreboot.rom add -t microcode -n cpu_microcode_blob.bin -b <base address> -f cpu_microcode_blob.bin</code></pre>
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</li>
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<li>Set the Kconfig values
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<ul>
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<li>CONFIG_CPU_MICROCODE_CBFS_LOC set to the value from the previous step</li>
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<li>CONFIG_CPU_MICROCODE_CBFS_LEN</li>
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</ul>
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</li>
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</ol>
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</li>
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<li>Debug the result until port 0x80 outputs
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<ol type="A">
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<li>0x90: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205">POST_FSP_TEMP_RAM_INIT</a>
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- Just before calling
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<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l73">TempRamInit</a>
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</li>
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<li>0x2A - Just before calling
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<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l151">cache_as_ram_main</a>
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which is the start of the verstage code which may be part of romstage
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</li>
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</ol>
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</li>
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</ol>
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<hr>
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<h1><a name="Romstage">Romstage</a></h1>
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<h2><a name="SerialOutput">Serial Output</a></h2>
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<p>
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The following steps add the serial output support for romstage:
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</p>
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<ol>
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<li>Create the romstage subdirectory</li>
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<li>Add romstage/romstage.c
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<ol type="A">
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<li>Program the necessary base addresses</li>
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<li>Disable the TCO</li>
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</ol>
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</li>
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<li>Add romstage/Makefile.inc
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<ol type="A">
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<li>Add romstage.c to romstage</li>
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</ol>
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</li>
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<li>Add gpio configuration support if necessary</li>
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<li>Add the necessary .h files to support the build</li>
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<li>Update Makefile.inc
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<ol type="A">
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<li>Add the romstage subdirectory</li>
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<li>Add the gpio configuration support file to romstage</li>
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</ol>
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</li>
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<li>Set the necessary Kconfig values to enable serial output:
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<ul>
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<li>CONFIG_DRIVERS_UART_<driver>=y</li>
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<li>CONFIG_CONSOLE_SERIAL=y</li>
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<li>CONFIG_UART_FOR_CONSOLE=<port></li>
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<li>CONFIG_CONSOLE_SERIAL_115200=y</li>
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</ul>
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</li>
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</ol>
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<h2><a name="PreviousSleepState">Determine Previous Sleep State</a></h2>
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<p>
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The following steps implement the code to get the previous sleep state:
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</p>
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<ol>
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<li>Implement the fill_power_state routine which determines the previous sleep state</li>
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<li>Debug the result until port 0x80 outputs
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<ol type="A">
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<li>0x32:
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- Just after entering
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<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/romstage.c;hb=HEAD#l99">romstage_common</a>
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</li>
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<li>0x33 - Just after calling
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<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/romstage.c;hb=HEAD#l113">soc_pre_ram_init</a>
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</li>
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<li>0x34:
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- Just after entering
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<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l67">raminit</a>
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</li>
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</ol>
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</ol>
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<h2><a name="MemoryInit">MemoryInit Support</a></h2>
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<p>
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The following steps implement the code to support the FSP MemoryInit call:
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</p>
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<ol>
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<li>Add the chip.h header file to define the UPD values which get passed
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to MemoryInit. Skip the values containing SPD addresses and DRAM
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configuration data which is determined by the board.
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<p>
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<b>Build Note</b>: The src/mainboard/<Vendor>/<Board>/devicetree.cb
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file specifies the default values for these parameters. The build
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process creates the static.c module which contains the config data
|
|
structure containing these values.
|
|
</p>
|
|
</li>
|
|
<li>Edit romstage/romstage.c
|
|
<ol type="A">
|
|
<li>Implement the romstage/romstage.c/soc_memory_init_params routine to
|
|
copy the values from the config structure into the UPD structure
|
|
</li>
|
|
<li>Implement the soc_display_memory_init_params routine to display
|
|
the updated UPD parameters by calling fsp_display_upd_value
|
|
</li>
|
|
</ol>
|
|
</li>
|
|
</ol>
|
|
|
|
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|
<hr>
|
|
<p>Modified: 31 January 2016</p>
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|
</body>
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|
</html> |