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Mike Loptien d0167d3ae2 MP Spec: Correct the Virtual Wire assignment
Virtual Wire mode is set by writing 0 to the the MPTable
Feature2 bit field 'IMCR'.  The virtualwire variable was
initially defined as writing a 1 to this bit field which
would actually set PIC mode instead of Virtual Wire mode.
However, nearly every mainboard called the MPTables with
virtualwire = 0, which actually had the effect of setting
Virtual Wire mode. I am correcting the definition but
leaving the call to write the MPTables with virtualwire = 0,
which is how most mainboards are already setting the tables
up.

See the MP Spec table 4-1 for more details:
	Bit 7: IMCRP. When the IMCR presence bit is
	set, the IMCR is present and PIC Mode is
	implemented; otherwise, Virtual Wire Mode is
	implemented.

http://download.intel.com/design/archives/processors/pro/docs/24201606.pdf

Change-Id: I039d88134aabd55166c2b68aa842bacbfcc0f42b
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/5977
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-16 18:14:35 +02:00
3rdparty@45f0c04fd7 acpigen: Add acpigen_emit_eisaid. 2014-06-01 01:24:53 +02:00
documentation Drop drivers/generic/debug 2014-04-22 13:42:48 +02:00
payloads payloads/external/SeaBIOS: Upgrade stable from 1.7.2.1 to 1.7.4 2014-05-28 22:41:59 +02:00
src MP Spec: Correct the Virtual Wire assignment 2014-06-16 18:14:35 +02:00
util util/inteltool: Add pci ids for 4 northbridge models instead of 1. 2014-06-11 03:05:01 +02:00
.gitignore git-ignore site-local 2014-04-01 08:55:02 +02:00
.gitmodules gitmodules: Fix 3rdparty updates 2013-06-28 00:56:43 +02:00
.gitreview add .gitreview 2012-11-01 23:13:39 +01:00
COPYING update license template. 2006-08-12 22:03:36 +00:00
Makefile build system: re-enable clang use 2014-05-26 09:23:55 +02:00
Makefile.inc build system: re-enable clang use 2014-05-26 09:23:55 +02:00
README Update README with newer version of the text from the web page 2011-06-15 10:16:33 +02:00
toolchain.inc build: use CFLAGS_* in more places where they're needed 2014-05-19 15:21:52 +02:00

README

-------------------------------------------------------------------------------
coreboot README
-------------------------------------------------------------------------------

coreboot is a Free Software project aimed at replacing the proprietary BIOS
(firmware) found in most computers.  coreboot performs a little bit of
hardware initialization and then executes additional boot logic, called a
payload.

With the separation of hardware initialization and later boot logic,
coreboot can scale from specialized applications that run directly
firmware, run operating systems in flash, load custom
bootloaders, or implement firmware standards, like PC BIOS services or
UEFI. This allows for systems to only include the features necessary
in the target application, reducing the amount of code and flash space
required.

coreboot was formerly known as LinuxBIOS.


Payloads
--------

After the basic initialization of the hardware has been performed, any
desired "payload" can be started by coreboot.

See http://www.coreboot.org/Payloads for a list of supported payloads.


Supported Hardware
------------------

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

 * http://www.coreboot.org/Supported_Motherboards
 * http://www.coreboot.org/Supported_Chipsets_and_Devices


Build Requirements
------------------

 * gcc / g++
 * make

Optional:

 * doxygen (for generating/viewing documentation)
 * iasl (for targets with ACPI support)
 * gdb (for better debugging facilities on some targets)
 * ncurses (for 'make menuconfig')
 * flex and bison (for regenerating parsers)


Building coreboot
-----------------

Please consult http://www.coreboot.org/Build_HOWTO for details.


Testing coreboot Without Modifying Your Hardware
------------------------------------------------

If you want to test coreboot without any risks before you really decide
to use it on your hardware, you can use the QEMU system emulator to run
coreboot virtually in QEMU.

Please see http://www.coreboot.org/QEMU for details.


Website and Mailing List
------------------------

Further details on the project, a FAQ, many HOWTOs, news, development
guidelines and more can be found on the coreboot website:

  http://www.coreboot.org

You can contact us directly on the coreboot mailing list:

  http://www.coreboot.org/Mailinglist


Copyright and License
---------------------

The copyright on coreboot is owned by quite a large number of individual
developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL).
Some files are licensed under the "GPL (version 2, or any later version)",
and some files are licensed under the "GPL, version 2". For some parts, which
were derived from other projects, other (GPL-compatible) licenses may apply.
Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.